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PSS 3.1 Channels: The Game Changer for Target-Time Communication
Portable Stimulus models already feature powerful language constructs to describe scenario intent. Activities, constraints, resources, buffers, streams, and states let the Perspec solver build a legal...
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Why 10BASE-T1S Automotive Ethernet SoC Verification Needs More Than Simulation?
Cadence Multi-Platform Verification improves functional coverage and verification time The recent advancements in the automotive industry, such as ADAS/AV, and infotainment all depend on reliable...
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Understanding PCIe 6.0 Power States: L0p vs L0s vs L1
PCI Express has always focused on a single goal: maximizing performance while minimizing power. However, with PCIe 6.0, maintaining this balance has become far more challenging. With PAM4 signaling in...
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From Pacemakers to ADAS: Verifying Systems Before Tapeout
Imagine discovering a critical bug in a heart pacemaker, not after deployment, not during final qualification testing, but months before the chip itself exists.At first glance, that sounds impossible....
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DFI 6.0 Key Highlights of the Latest DFI Specification
The DDR PHY Interface (DFI) protocol specifies the signals, timing parameters, and configurable options necessary for the transfer of command information and data across the DFI, facilitating...
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UALink Under the Hood: Why Full-Stack Verification Wins
Inside the UALink stack: How 640 bytes travel from intent to wire, and why full-stack verification catches what layer testing misses.(read more)
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NVMe 2.0 Explained: What’s New and Why It Matters
Non-Volatile Memory Express (NVMe) has become the dominant protocol for high-performance storage across client SSDs, enterprise drives, and hyperscale data centers. With NVMe 2.0, the specification...
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Understanding USB4 Retimers and Their Role in Gen2 and Gen3 - Link Training
USB4 systems rely on retimers to enable reliable high-speed communication across complex topologies where maintaining signal integrity over extended channels is a significant challenge. Retimers act as...
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The Infineon Automotive Ecosystem Summit 2026
The 2026 Infineon Automotive Ecosystem Summit took place in late June at the Infineon headquarters at am Campeon in Munich. The event brought together the ecosystem around Infineon's automotive...
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Demystifying Address Translation Services (ATS) in PCIe 6.0
Address Translation Services (ATS) is one of the toughest verification problems to solve as it is the fast lane for PCIe memory access, cutting delays by caching address translations directly on the...
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Enhancing Ethernet Security with MACsec
Understanding MACsec in Today’s Ethernet WorldToday, Ethernet is being widely adopted across domains ranging from high-performance computing (HPC) and cloud data centers to automotive systems, where...
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Ethernet Auto-Negotiation: Enabling Seamless Link Optimization
Ethernet has evolved significantly from 10 Mbps shared media to today’s multi-hundred gigabit high-speed links. One foundational feature that has enabled this scalability and ease of deployment is...
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DDR5 MRDIMM: A Transformational Evolution for DDR5 DIMM
DDR5 is the latest generation of DDR server memory capable of supporting data rates of up to 9,200Mbps, which is a huge leap over the previous generation of DDR memories. It is used in a wide variety...
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Controller Memory Buffer (CMB): NVMe 2.0’s On-Controller Memory Feature
Non-volatile Memory Express (NVMe) has become the dominant interface protocol for high-performance storage devices. As workloads demand ever-lower latencies, the NVMe specification has evolved with...
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Inside Akeana and Cadence’s Secret Sauce for Faster RISC-V Chip Verification
The Nightmare of Chip Testing (And How to Fix It)Let's be real: designing ambitious new RISC-V chips is cool, but testing them is an absolute nightmare. When you are building crazy complex pipelines...
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Cadence Announces PCIe 8.0 Verification IP Availability at PCI‑SIG US
At the recent PCI‑SIG Developers Conference US held on May 6-7,2026, Cadence announced the availability of its PCIe 8.0 Verification IP (VIP)—taking another significant step in enabling early,...
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VLAB at the MATLAB Expo Japan 2026
The Cadence VLAB team will be part of the Cadence team present at the MATLAB Expo Japan on May 26 in Tokyo. We will be demonstrating how MATLAB and Simulink models can be used to co-simulate with VLAB...
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Unraveling Precision Time Measurement (PTM)
IntroductionPrecision Time Measurement (PTM) is an optional capability for communicating precise timing information between components. PTM enables precise coordination of events across multiple...
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Unraveling Embedded Clock Mode in MIPI D-PHY: Simplifying High-Speed Serial Link
As flagship smartphones push camera sensors beyond 200 megapixels and display resolutions beyond 4K, and as automotive applications demand ever-higher bandwidth, the physical layer interfaces...
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Struggling to Rewrite Functionality in PSS? Import Functions Streamlines
One of the most powerful features of the Portable Stimulus Standard (PSS) is the ability to import functions from foreign languages like C or SystemVerilog. This capability is far more than a...
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