At Hewlett-Packard Enterprise (HPE), the team working to create IP for “The Machine,” HPE’s vision for the future of computing, recently decided to make the switch to the Xcelium Simulator from their old mix of simulators. To gauge how much Xcelium would help improve their productivity, engineers at HPE devised a series of trials. Each trial applied a specific set of circumstances to check how Xcelium would perform in their environments—and Xcelium performed.
The first trial was a direct upgrade from Incisive 15.20 to Xcelium, on a simple build flow. Since Xcelium has irun mapped to xrun, all the engineers had to do to update it was simply point their tests from the old Incisive to the new Xcelium. Even something as quick and easy as that still saw a 15% system performance increase—and that’s just with single-core! In the future, HPE plans to migrate some of their gate models to test Xcelium’s multi-core simulation capabilities.
Another trial was to take tests that ran on a non-Cadence simulator, and run them on Xcelium. These were UVM-SV tests, with third-party-created build scripts, and they ran in both block-level and SoC environments. Even with only initial tuning and training, the team still saw a 25% increase in performance for block-level tests.
The final trial was, again, moving the tests from another non-cadence simulator to Xcelium; but this time, the tests ran on a C++ based testbench. Those tests ran in block-level and chip environments, and the block-level tests in that trial ran 20% faster than before.
Going forward, HPE plans to continue to train their engineers in using Xcelium, and they’ll be working with Cadence to do additional tuning to their unique simulation needs.
To watch the presentation given by HPE on their experiences with Xcelium at DAC 2017, click here.
