App Note Spotlight: SystemVerilog Gets a Real Number Modeling Update (SVRNM)

Thanks to Xcelium, there’s a new feature on the block in SystemVerilog. It pertains to real number modeling (SVRNM), and it both enhances and simplifies the design of mixed-signal circuits.

How? Well, for example, in the process of pixel design for image sensors, a designer may need to have several real nets share a value at the same time. This effectively makes those nets shorted together for the required duration—along with that, the opposite is true: if two nets don’t share a value, they’re effectively disconnected. Before, this switch-level modeling wasn’t possible, and pixel design was an incredibly tedious process, rife with trial-and-error to reach coverage signoff.

But now, SystemVerilog RNM can now short or disconnect nets at any specified time, which greatly accelerates testing, and allows for more specific and accurate tests to be run.

On top of that, as with most features in SystemVerilog RNM, it can be used in both digital contexts and mixed-signal contexts.

To use the new database associated with the app note, a working knowledge of AMS-Designer Xcelium Use Model (AXUM) and the SimVision graphical user interface is helpful. Also, only the 17.04+ releases of Xcelium can run the database.

This database has six key files. Here’s a basic description of what they all do.

1. force_rel.sv: This defines a 2D real array. It outputs two one-dimensional arrays.
2. force_rel.tcl: This collection of TCL commands controls the sim run. It loads values into the array defined by force_rel.sv.
3. wtranif1.svp: Essentially the tranif1 primitive, except it works with real nets.
4. wreal_avg.sv: This takes the two one-dimensional arrays outputted by force_rel.sv and outputs two arrays of a predefined ‘nettype’ called wrealavg.
5. top.sv: Provides top-level connectivity.
6. xrunSc: This is an xrun-based script used to start the test case. It doesn’t need any specific options or settings.

For More

What's mentioned here is only the start of what this update holds. If you want to learn more, check out the app note on the new update to SystemVerilog RNM here.

If you thinking to yourself “how can I do that verification thing?”, send me an email at tyler@cadence.com or post a comment here describing that “verification thing.” I’ll work with our engineers to see if we have an app note already, or if we don’t, we can create one. Otherwise, check back in two weeks for another app note spotlight!