Welcome to the App Note Spotlight—a bi-weekly series where the XTeam highlights an app note that contains valuable information you may not be aware of. Today, we're going to look at connect modules—what they are, and why you should care about them.
A Quick Run-Down on Connect Modules
To understand connect modules, we'll need to step back a bit. First, understand that mixed-signal simulation has to happen in both analog and digital contexts. Analog signals are continuous, which means they can’t be described by simply using 0 or 1. They could be anywhere in between, so they’re described as “continuous.” Moreover, analog signals in a design may have a completely different range than the voltages used to represent the digital values. Digital signals functionally have two discrete states in most circuits —on or off—so they’re referred to as just that, “discrete.” Since the real world is analog, digital states also include X, Z, strengths, and digital signals can have other states, but those are all attributes of the 0 and 1.
Now, mixed-signal simulation has to traverse these incompatible domains—so there must be some method of translating analog signals to digital ones and vice versa. This is what connect modules do.
Connect modules are Verilog-AMS or SV-RNM (SystemVerilog Real Number Model) modules designed to translate signals between discrete and continuous domains. They can be varyingly complex based on whatever the need is, but have the capabilities to accommodate any required adjustments, like input threshold delays, output impedance, power supply sensitivity, and more. They are often classified by their points of view: supply, modeling accuracy, or electrical property.
Depending on the mixed-signal simulation at hand, connect modules may have different requirements. They need to be able to get the supply signal in a static or dynamic way, handle either potential or flow, and need to reflect or inherit port impedance.
Basic Terms
Here’s some basic terminology you might need to understand connect modules:
Discipline: A Verilog-AMS language declaration used to define whether a domain is continuous or discrete. Disciplines define nodes, ports, and branches.
Nature: This describes individual signal types. Disciplines then pair those signals so they can more easily be used in the declaration of nodes, ports, or branches. These are defined in the disciplines.vams file.
Connect Module Placement
Now, you can’t just stick a connect module anywhere you want. Automatically, a connect module is inserted just after the Discipline Resolution (DR) process. However, you need to define two things before that automatic insertion can run and have the connect module function properly: connect modules and connect rules. Verliog-AMS LRM defines these items as a part of the language standard. Connect modules will never be inserted in the middle of a wire or net; only on a module or cell view boundary port.
A couple of factors can affect where a connect module is placed. They have to be between analog nets and digital nets; but certain things can mess with the specific location of the connect module. These include the DR algorithm used in simulation, the disciplines used to declare the nets explicitly, hierarchical IE and DR optimization, and the value of connect_mode’s attributes used in connect statements.
For More
There’s a lot more to see in regards to connect modules. If you want to learn more, check out the app note titled: "Introduction to Connect Modules."
If you thinking to yourself “how can I do that verification thing,” send me a email at tyler@cadence.com or post a comment here describing that “verification thing.” I’ll work with our engineers to see if we have an app note already, or we can create one. Otherwise, check back in two weeks for another app note spotlight!