As the device frequencies and the data rates go up with every new generation of Interface and memory devices, sampling of the signals and the transferring of the data b/w Initiator and target is being increasingly difficult with ever shrinking data eyes.
To assist with handshaking for the high speed I/O, most of the newer generation of the interfaces and memories support an ever-increasing number of Training Modes that the system designer has to consider as part of system bring up/operation for systems to work as intended and to make sure Initiator and target are able to communicate with each other.
This is an even more important problem for new generations of DRAM memories that latest SOC SoC use.
Here are categories of the most important Trainings supported by latest DRAMs like LPDDR5 and DDR5/DDR5 DIMMs: -
1. Vref Training
This is the part of initial bring up of the memory subsystem. Host will typically set the DRAM mode register that will be used for reference voltage for signals like command, chip select and DQ. Since the DRAM may not be able to sample the Host command at the time Vref training is done, Host sends it over multiple cycles to make sure that DRAM is able to receive it.
2. Command Training
This is typically the first functional Training that the Host has to perform to make sure that the DRAM device is able to understand the Commands that it is intending to send. It involves the Host driving DRAM’s command bus which thanthen samples and sends what it receives as feedback on DQ signals. Host can check the feedback and compare with what it drove. Host can than then adjust the input if the feedback doesn’t match what was driven.
3. Clock to Strobe leveling
Due to routing differences b/w different signals and other factor, the strobe signals that DRAM usages will typically not be aligned to the input clock that it receives. The Host must adjust for this phase difference by going through Clock to Strobe leveling. This training is referred to as External/Internal Write leveling for DDR5 and WCK2CK leveling for LPDDR5 (and just write leveling for previous generations of memories like LPDDR4,DDR4 etc).
4. Strobe to DQ Training
Once the Clock to Strobe training is done, the next step is making sure Host and DRAM are able to send/sample write and read data correctly. Aim for this step is for Host to know the timing relationship b/w the strobe and the data signal and is referred to as Strobe to DQ training. It typically involves sending of a known data written to the DRAM followed by reading from the same location and comparison of the two to check if it matches. Host then adjusts its strobe to the Data signal delay and goes through the same step again till it’s able to send/receive the write/read data to/from DRAM correctly.
5. Other Trainings
There are several other trainings that are supported to help with specific functionality of device. For device modules like DDR5 DIMMs, the training not only involves the individual components (RCD, DRAM, DB) but how the signals are propagated from one component to another. Host is required to train the individual component as well as the module as a whole. Some of the DDR5 LRDIMM trainings like MRE, MRD, DWL, MWD, etc. are good examples of the module level trainings.
In summary, trainings are a big part of system bring up and normal function. It is also increasingly becoming a significant design and verification challenge that needs to be accounted for as part of planning for SOC.
Cadence MMAV VIPs for DDR5/DDR5 DIMM and LPDDR5 are compressive VIP solutions and supports all of the above-listed Training Modes. LPDDR5 & DDR5 VIPs also support additional configurable knobs to control VIP behavior on training error to assist with the verification challenges arising out of testing for these trainings.
More information on Cadence DDR5/LPDDR5 VIP is available at Cadence VIP Memory Models Website.