We covered CHI specification revisions A to D in my previous article, what about Issue E?
Issue E was by far the biggest update yet with a slew of new transactions, optimization features to interface behavior and architecture, and spec clarifications and corrections. It spanned two years and two sub releases (E.a and E.b).
2020 (CHI-E.a) Issue E.a – update
Issue E.a added new transaction types such as Write*Zero, SnpQuery, MakeReadUnique(Excel), and two-part Stash to more efficiently move data and manage caches.
New Direct Write Transfer (DWT) permitted the Requester to send data directly to the Subordinate therefore reduced DAT channel and Home node usage. Write transactions with Cache Maintenance transactions avoided the need to serialize Write and (P)CMO transactions. Both optimized pipelining.
Issue E.a also offered interface enhancements. Multiple Interfaces increased available bandwidth by duplicating the complete interface. Replicated Channels increased available bandwidth by replicating only the channels that required more bandwidth.
CHI specs:
“Multiple Interfaces - The simplest method for a component to increase the available bandwidth is to have multiple interfaces.”
“Replicated Channels on a Single Interface - A more efficient method to increase the available interface bandwidth, rather than replicating a complete interface through more complex methods, is to selectively replicate the channels that require greater bandwidth.”
In Issue D the TxnID width increased to 10. It jumped again to 12 in Issue E, with the number of outstanding transactions limited to 1024.
Arm was not done, enhancements like Memory Tagging improved the architecture.
CHI specs:
“The Memory Tagging Extension (MTE) is a mechanism that is used to check the correct usage of data held in memory.”
“This mechanism ensures that a memory access is for its expected purpose, rather than an erroneous or malicious access. The mechanism can be used at run-time to identify many common programming memory errors, such as buffer overflow and use-after-free.”
MTE compared Physical Address Tag against Allocation Tag locations to determine correct usage of data in memory. To support this, Tag, Tag Update (TU), and Tag Operation (TagOp) bits were added.
2021 (CHI-E.b) Issue E.b - update
Issue E.b mainly clarified and corrected numerous aspects of the specification.
Arm’s commitment to progressive terminology should be noted here. Potentially offensive terms were replaced throughout this specification.
CHI specs:
“Arm values inclusive communities. Arm recognizes that we and our industry have used terms that can be offensive.
Arm strives to lead the industry and create change. Previous issues of this document included terms that can be offensive.
We have replaced these terms.”
Full specifications and revisions at Arm: AMBA 5 CHI Architecture Specification.
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