Overview of PCIe 7.0 Technology
PCIe technology has evolved over three decades, marking its 30th anniversary with the unveiling of PCIe 7.0. This latest standard doubles IO bandwidth to 128GT/s, emphasizing low latency and high reliability while maintaining compatibility with previous generations. Key features on the physical layer include the adoption of PAM4 signaling, 1b/1b encoding, and a robust Forward Error Correction (FEC) mechanism same as PCIe 6.0.
PCIe 7.0 provides IO bandwidth of 128GT/s
Industry Adoption Trends
PCIe 7.0 is set to see rapid adoption, driven by its streamlined transition from PCIe 6.0. The market has already witnessed the release of PCIe 7.0 SerDes test chips and testing equipment following the introduction of PCIe 7.0 rev0.5 in February 2024. With PCIe 7.0 rev1.0 expected to be finalized by mid-2025, the standard is poised to meet the escalating bandwidth needs of AI/ML, Cloud, HPC, and other demanding applications.
Cadence Verification IP Offering
Cadence Verification IP provides support for PCIe Gen7 rev0.5 specification, which can be utilized for IP, sub-system, and SoC-level verification testbenches. Cadence Verification IP- PCIe Gen7 supports the following features:
- PAM4 with Serial Interface
- Link Width support for x1, x2, x4, x8, x16
- Clock frequency 128.0 GT/s
- EIEOSQ Ordered Set for 128.0 GT/s
- 1b/1b encoding, FEC, and CRC
- Flit Mode inherited from PCIe 6.0
- Protocol behavior for the transaction layer, data link layer, and logical physical layer is the same as PCIe 6.0
- System-level features like Integrity and Data Encryption (IDE), Data Object Exchange (DOE), Single Root IO Virtualization (SR-IOV), etc.
- Maintains backward compatibility with all previous generations
- Applicable for device types root complex and endpoint
Cadence offers a comprehensive suite including protocol checkers, functional coverage, an integrated verification plan, and a standard UVM-compliant demo example for PCIe 7.0, aimed at accelerating the bring-up process for new users. The Cadence Verification IP for PCIe 7.0 is optimized to facilitate seamless migration from PCIe 6.0, minimizing transition efforts for existing users' testbenches.
Cadence Verification IP supports layer-wise callbacks that are accessible in the testbench for scoreboarding and data manipulation. Additionally, the PCIe waveform Debugger is integrated with the VIP to present transactions, configuration space registers, and signals within the same interface, facilitating efficient debugging. Furthermore, the VIP offers pre-configured per-layer packet trackers that can be customized for user-defined packet fields.
PCIe 7.0 demo in Cadence VIP install path showing successful L0 transition at Gen7 speed
Conclusion
Cadence has started collaborating with early adopters for PCIe 7.0 on Serdes IPs, which are in the market before compatible controllers, switches, and fabrics are out.
We are eagerly looking forward to engaging with more customers as the ecosystem around PCIe 7.0 grows.
- For more info on how Cadence PCIe Verification IP and TripleCheck VIP enable users to confidently verify PCIe designs, see our product pages on VIP for PCI Express, and TripleCheck for PCI Express
- Refer PCI-SIG website for more details on PCIe in general and upcoming revisions on PCIe 7.0