The Cadence Palladium Emulation Platform is a hardware system that implements the design, accelerating its execution and verification. Itoffers the highest performance and fastest bring-up times for pre-silicon validation of billion-gate designs, using a custom processor built by Cadence.
This Palladium Introduction course is based on the Palladium 23.03 ISR4 version and covers the following modules:
- Introduction
- Palladium flow
- Running a design on the Palladium system
This course starts with an “Introduction” module that explains Palladium and other verification platforms to show its place in the big picture. It also compares Palladium with Protium and simulation and discusses its usage and limitations.
The “Palladium Flow” module includes two stages at a high level, which are Compile and Run. Then, it covers these stages in detail. First, it covers the ICE compile flow and IXCOM compile flow steps in detail. Then it explains Run, which is common for both ICE and IXCOM modes.
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The third module, “Running Design on the Palladium System,” covers all the items required for running your design on the Palladium system, including:
- Software stack requirements
- Basic concepts required to understand the flow
- Compute machine requirements
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In addition, this course contains labs for both the ICE and IXCOM flows with detailed steps to exercise the features provided by the Palladium system. The lab explains a practical example of multiple counters and exercising their signals for force, monitor, and deposit features, along with frequency calculation using a real-time clock. The course is available on the Cadence support page:
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There is also a Digital Badge available. You will find the Badge exam opportunity when you enroll in the Online training or after you have taken the training as "live" training.
For questions and inquiries, or issues with registration, reach out to us at Cadence Training. Want to stay up to date on webinars and courses? Subscribe to Cadence Training emails. To view our complete training offerings, visit the Cadence Training website.
Related Training Bytes
- Palladium: What Are Verification Platforms
- Palladium: What Is Processor Based Emulation
- Palladium: Comparing Emulation (Z2) and Prototyping (X2)
- Palladium: What Are ICE and IXCOM Compile Flow
- Palladium: How to Process a Design to Run on Palladium
- Palladium: XCOM Compile Flow (TB+RTL to Palladium Database)
- Palladium: ICE Compile Flow (RTL to Palladium Database)
- Palladium: Legacy ICE Compile Flow
- Palladium: Cadence Software Releases for Palladium and Protium Flow
- Palladium: Setting of PATHs for Using Palladium
- Palladium: Z2 Hardware Structure (Blade and Boards)
- Palladium: What Is Sourceless and Loadless nets
- Palladium: Design Clocks
- Palladium: Step Count and Step Clock
- Palladium: Steps for Running the Design on Palladium Z2
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