Cadence is well-known for supporting PCIe technology and providing a robust ecosystem. The PCI-SIG Developers Conference India 2024 was designed as a two-day event held in Bengaluru on November 11th and 12th, 2024. Cadence is involved in various aspects of the PCI-SIG Developers Conference, including being part of the sponsor team. Cadence set up a booth to represent work on PCIe Gen 7.
Image may be NSFW.
Clik here to view.
Cadence Booth Demonstrations in PCI-SIG
- Hardware demonstration of the feasibility of PCIe 7.0 physical layer speed of PMA-128Gbps in collaboration with Keysight Technologies
- PCIe 7.0 VIP example demonstration using a VIP back-to-back environment
- Paper presentation on effective PCIe 6.0 switch performance verification
- Paper presentation on the challenges of partial header encryption in PCIe 6.0 in collaboration with Google
PCIe 7.0 Physical Layer Hardware Demonstration
The hardware demonstrates the capability of providing advanced solutions for PCIe Gen 7 to prove that our 5nm technology bird Sparrow C2 can operate at a 128Gbps data rate and give promising results with respect to both the transmitter and receiver.
The transmitter setup involved a direct connection to the scope using a test fixture of 6in MXPM and the PCB traces, which were de-embedded. Thus, only a transmitter package loss of 3dB was considered in the path.
Using the bessel filter with a bandwidth of 64GHz and transmitting a PRBS9 pattern at a data rate of 128Gbps from our Sparrow C2 test chip to the Keysight UXR Series Scope, which acted as the receiver for our transmitter, we successfully showed the signal at 128Gbps with a wide open PAM4 EYE diagram.
The receiver end includes calibration of the BERT swing to 800mV and a channel of 28dB loss added as the path from the BERT to the test chip receiver bump. To represent the worst-case ISI scenario, transmitted a PRBS31 pattern to the receiver and monitored the real time BER of ~3e-8.
Image may be NSFW.
Clik here to view.
Image may be NSFW.
Clik here to view.
PCIe 7.0 VIP Back-to-Back Environment
In the demo, the configuration of PCIe VIP is done to support 7.0 in serial PAM4 mode using PureView tool. Sample testbench files can be picked from the VIPCAT deliverable example. During the execution of the sanity testcase, memory transactions are initiated by RC VIP after the Gen 7 linkup. After reading from the same memory location where the write has happened, the correctness is checked to verify the functionality.
After execution, output log files are analyzed for LTSSM states, link width, PCIe capabilities, packets in packet tracker file, and waveform analysis using Verisium Debug tool. All the tools demonstrated are very effective during debugging.
The demo shows the PCIe testbench environment to test the DUT. Here, PCIe Gen 7.0 VIP is connected back-to-back, and any VIP can be replaced with user DUT.
Image may be NSFW.
Clik here to view.
Paper Presentation – Effective PCIe 6.0 Switch Performance
(The link works only for PCI-SIG members)
The "Effective PCIe 6.0 Switch Performance Verification" paper was presented by Deep Mehta and co-authored by Sangeeta Soni from the VIP Product Engineering team.
Cadence discussed the performance verification of PCIe 6.0 switches. The paper highlighted the importance of performance testing in uncovering corner-case bugs and demonstrated a traffic modeling approach that can identify these issues.
Additionally, the presentation discussed latency monitoring techniques using performance measurement utilities like Performance Banner and provided implementation guidelines. Suggested findings and methodologies have value beyond IP verification, extending to pre-silicon emulation and post-silicon validation.
Image may be NSFW.
Clik here to view.
Paper Presentation – Challenges of Partial Header Encryption in PCIe 6.0
(The link works only for PCI-SIG members)
This paper is presented by Ritesh Mehta from Google Cloud team, co-authored by Sagar Shah, Google, and Sangeeta Soni, Cadence Product Engineering team. It highlights the challenges of Partial Header Encryption (PHE) in PCIe 6.0. It began by providing a basic overview of IDE packet structure along with an explanation of what PHE is and why it is necessary. It also covers the mechanism to reduce exposure to side-band attacks. The paper also explores the different PHE modes and finally delves into the challenges of verifying PHE, including 64B address, PH enable, and MAC calculation.
Image may be NSFW.
Clik here to view.
Related Blogs
- Introducing PCIe's Integrity and Data Encryption Feature (IDE)
- Verification of Integrity and Data Encryption (IDE) for PCIe Devices
- Streamline PCIe 6.0 Switch Design with Effective Verification Strategies
- Why IDE Security Technology for PCIe and CXL?
Other Relevant Links
- Cadence Simulation VIP for PCIe
- Controller for PCIe | Cadence
- PCI-SIG Developers Conference material (only for PCI-SIG members)
This post has been authored by Sandeep Nasa and Sangeeta Soni.
Image may be NSFW.Clik here to view.