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Randomization considerations for PCIe Integrity and Data Encryption...
Peripheral Component Interconnect Express (PCIe) is a high-speed interface standard widely used for connecting processors, memory, and peripherals. With the increasing reliance on PCIe to handle...
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USB4 Sideband Channel Is Not a Side Business
The USB4 specification has been around for several years now. Two years ago, USB4 version 2.0 was also released by the USB Promoter Group. This specification enables up to 80Gbps link speed per...
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Cadence PCIe 7.0 Solution at PCI-SIG Developers Conference India 2024
Cadence is well-known for supporting PCIe technology and providing a robust ecosystem. The PCI-SIG Developers Conference India 2024 was designed as a two-day event held in Bengaluru on November 11th...
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Audio Transport in DisplayPort VIP
DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports...
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Introduction of High Bandwidth Embedded USB2v2 (eUSB2v2) Standard
Universal Serial Bus (USB) technology is the most popular connector in every computing device, but when it comes to embedded applications, where only a specific device function may be required, the...
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Unraveling Orthogonal Header Content (OHC) in PCIe 6.0
Introduction With the arrival of Flit Mode, the information hold by the TLP header was reorganized. In addition to the base header, Orthogonal Header Content (OHC) may be added into the TLP. OHC works...
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Various Types of Transaction-Based Interfaces (TLM) for DisplayPort VIP
IntroductionDifferent RTL designs often require different specially designed parallel interfaces. These different interface requirements serve varying needs, such as certain blocks not being ready when...
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Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
As technology continues to advance, so do the ways we connect and manage memory and devices in our computing systems. The latest version of Compute Express Link (CXL) 3.1 introduces a feature known as...
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AMBA LTI Verification IP for Arm System MMU
The AMBA LTI (Local Translation Interface) defines the point-to-point protocol between an I/O device and the TLBU (Translation Buffer Unit) of an Arm System Memory Management (SMMU). The LTI protocol...
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Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in August 2024, which is developed to deliver a scalable I/O technology, specifically designed for inside-the-box...
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Cadence's 2024 Training Programs and Resources
As we welcome 2025, let’s take a moment to reflect on the most viewed blogs and videos of the past year and review the developments in education throughout 2024.During 2024, we released eight...
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Time on Your Side: Launching PSS Perspec Composer
We all agree that time is precious. As PSS (Portable Stimuli Standard) models get larger, the time it takes for the whole model to be loaded in Cadence Perspec Composer might become meaningful. In this...
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USB4 Port Operations
Designs are tested in the labs for various electrical compliance tests defined in the electrical compliance test specifications before getting certified. There are defined processes and steps that a...
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Training Insights – Tcl Scripting Course for Beginner and Advanced Users
Tcl is a versatile scripting language used in automation, testing, networking, and more. Tcl plays a crucial role in Electronic Design Automation (EDA) tools used in the VLSI industry.Leading EDA tools...
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Unlocking Efficient Debugging with the Verisium WaveMiner App
Overview of the Verisium WaveMiner AppVerisium WaveMiner is part of the Verisium suite of AI-driven verification tools that automate the root cause analysis of misbehavior introduced between two...
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