The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos.

13. Interface UVC Environment
14. Virtual Sequencer - Sequence
15. Module UVC
16. Scoreboard
17. DUT Functional Coverage
18. Testbench
19. Test
20. Configuration
21. Factory
22. Phases
23. Objections
24. Virtual Interface
25. Class Library Overview

Once more I would like to thank my colleague, Yih-Shiun Lin for his great job in translating the audio. It is his voice you hear on these videos.

Besides releasing the videos to YouTube, we are also publishing them on

YouKu, the Chinese version of YouTube.

Link to YouTube Playlist (Chinese)

Link to YouKu Playlist (Chinese)

Link to YouTube Playlist (English)

Link to YouKu Playlist (English)

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer