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The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics”...
In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos. Interface UVC Environment Virtual...
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What Does it Take to Migrate from e to UVMe?
So you are developing your verification environment in e, and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to...
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UVM Testflow Phases, Reset and Sequences
In this post, we will discuss the interesting challenge of reset during simulation.Specman has a very robust implementation of reset during test, which imitates a return to cycle 0. All threads are...
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Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A...
Right up there with functional verification, the challenges of low power design and verification present an existential threat to our customers' products, and ultimately their businesses. Clearly both...
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Speed of “Light” – My First iPhone 5 Impression
So what’s the big deal with the iPhone 5? Some folks have commented: "It is just a bit faster, taller, lighter – no big deal." Let me tell you one thing: Seeing, no handling and touching is believing....
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Shameless Promotion: Free Club Formal San Jose (with Lunch) on Wednesday 10/17
Please join Team Verify and other design and verification engineers at the next "Club Formal" on the Cadence San Jose campus on Wednesday, October 17 at 11:30am. This free, half-day event (including...
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Using pli_access for Stubless Indexed Ports
Indexed ports are used to access composite HDL objects in SystemVerilog (SV). Their most frequent use is to access SV multi-dimensional arrays by defining a simple indexed port and accessing the array...
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Recorded Webinar: Using Metric-Driven Verification and Formal Together For...
[Preface: the upcoming "Club Formal" on October 17 here at the Cadence San Jose campus will also touch on this topic - please join us!]While it's now common knowledge that there are many benefits to...
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UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar
Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to...
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Do you MOOC? Expanding Access to e (IEEE 1647) Verification Training Globally
Two of the key factors for successful and productive simulation-based hardware verification are a efficient verification language and an associated methodology. As the global design and verification...
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Event Report: Club Formal San Jose – Features and Techniques for Experts,...
Last week over 35 power users from over a dozen companies came together for the latest installment of "Club Formal" -- a user group meeting exclusively focused on topics in formal analysis and...
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Function Level C Interface – New C Interface for Specman
Working with the conventional Specman C language interface has two major disadvantages:1. There is a tight dependency between the e code and the C code. The user must include the Specman header...
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Need e/Specman Expertise ASAP? Free Training and Verification Alliance...
Recently an EDA industry observer relayed some Specmaniacs' concerns about satisfying the increasing demand for e/Specman trained verification engineers in Europe and other geographies. Team Specman...
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UVM e vr_ad -- Specman Read/Write Register Enhancements
If you are a Specman vr_ad user, you probably know that register access is implemented using the read_reg / write_reg. For reading/writing a register, you have to 1. Extend a vr_ad_sequence2. Add a...
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New Product: ARM ACE Assertion-Based Verification IP (ABVIP) Available Now
As anyone who has worked with ARM's AMBA 4 AXITM Coherency Extensions -- a/k/a the "ACETM" protocol -- knows, there are a ton of different configuration options and operational scenarios available to...
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Techniques to Boost Incisive Simulation Performance
Functional verification is the biggest challenge in delivering more complex electronic devices on increasingly aggressive schedules. Every technique for functional verification relies on a fast...
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Avoid Overly Long Expressions in Specman e Code
When you write your e code, a good practice is to avoid expressions that are "overly long" even though they are completely legal. While there is no hard definition of what constitutes an overly long...
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Specman: Determining a Good Value for optimal_process_size
Specman's Automatic GC Settings mechanism is aimed at eliminating the need for users to control the parameters which determine each Garbage Collection's behavior. Setting config mem...
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2013 CES: Top 4 Trends Benefiting EDA
While a variety of EDA customer segments are growing, consumer electronics continues to drive the lion's share EDA of industry revenues. Hence, many events at last week's annual Consumer Electronics...
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Specman: An Assumed Generation Issue and its Real Root Cause
Random generation is always a complex task, and differences in results are usually very hard to debug. Besides, generation misbehavior always rings many bells in R&D :-)A customer reported a random...
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