If you are a Specman vr_ad user, you probably know that register access is implemented using the read_reg / write_reg. For reading/writing a register, you have to
1. Extend a vr_ad_sequence
2. Add a field of the type of the register you want to access
3. In the body() , call the read/write_reg
For example:
extend MAIN vr_ad_sequence {
!tx_data_reg : VR_AD_TX_DATA vr_ad_reg;
!tx_mode_reg : VR_AD_TX_MODE vr_ad_reg;
body() @driver.clock is only {
read_reg {.driver == reg_driver} tx_data_reg;
read_reg {.driver == reg_driver} tx_mode_reg;
};
};
For simplifying test writing, starting Specman 12.1 the read/write_reg actions can:
- Be called from any TCM, not only from within a sequence
- Access not only a local field, but also a variable, or a reference to a field within the e registers model
One of the nice capabilities achieved with these enhancements is that you can embed access to registers among other activities. For example -- in a system level sequence, as in this code example :
extend SEND_AND_CHECK system_seq {
!serial_frame : LEGAL frame;
body() @driver.clock is {
// Perform activity on serial interface, via the i/f driver
do serial_frame on driver.serial_driver;
// Local variable of a register, read it and check the value
var status_reg : STS vr_ad_reg;
read_reg {.driver == driver.reg_driver} status_reg;
check that status_reg.get_cur_value() == 0x37;
// Access registers without defining fields nor variables
write_reg {.driver == driver.reg_driver} driver.reg_model.reg0 val 0x12;
write_reg {.driver == driver.reg_driver} driver.reg_model.reg1 val 0xFA;
write_reg {.driver == driver.reg_driver} driver.reg_model.reg2 val 0x3;
write_reg {.driver == driver.reg_driver} driver.reg_model.reg3 val 0x0;
};
};
Note that register accesses are handled by the vr_ad_driver. So, when accessing a register from a TCM which is not a vr_ad sequence, you have to specify the vr_ad_driver to handle this operation.
We encourage you to check out the latest UVM e reference manual and user guide for details (both are part of Cadence Help).
Enjoy verification
Efrat Shneydor & Reuven Naveh,
UVM e