Functional verification is the biggest challenge in delivering more complex electronic devices on increasingly aggressive schedules. Every technique for functional verification relies on a fast simulation engine for execution, so performance is of prime importance to all users.
Simulation performance can't be a single number or optimization because each environment is unique in terms of the methodology deployed, the languages involved, the size of the design, and the verification environment.
Hence, Cadence Incisive performance team has developed a handbook to cover the major aspects of Simulator performance. It leads users to follow certain steps to better understand, and then address the performance need.
In many situations, the steps to localize the performance bottleneck and resolve it take a considerable amount of time. The application notes in the handbook help speed this process by giving you the information to improve performance. In the cases where you need more performance than the notes provide, they will guide you to create the well articulated and defined performance requirement making it easier for Cadence to optimize Incisive for speed.
Here is a series of application notes that focuses on areas (techniques and technologies), which helps you in improving the performance with Incisive Simulator.
| Topic and Link | Brief Description |
| Incisive Performance Analysis Checklist | A flow-based checklist to analyze the performance with Incisive Simulator |
| Top Focus Areas to maximize your simulation performance | Detailed analysis with Top causes for Performance bottlenecks. |
| Maximize Incisive Performance with Assertions | Assertions related guidelines and commands to help in Incisive performance analysis |
| Maximize Incisive Performance with Coverage | Coverage related guidelines and commands to help in Incisive performance analysis. |
| Analyzing Incisive Profiler for Performance | Understanding Profiler entries for better action-oriented performance analysis. |
| Maximize Incisive Performance with GLS | Describes command options, delays and timings check that can affect Gate-Level Simulation performance. |
| Incisive Debug Memory Consumption | Command options and utilities/steps to debug system memory consumption |
| Maximizing Productivity with Multi-Snapshot Incremental Elaboration MSIE Example | Describes a new technology, which allows a large, invariant, portion of the environment to be pre-elaborated and then shared with many varying tests. |
| Analyze UVM Environment Performance using Iprof | Describes the use model of the Incisive Advance profiler (Iprof) and how to use the profiler call graph reports to debug the performance bottlenecks of UVM based design verification environment. |
| Maximize Incisive Performance with SystemVerilog Randomization | Understanding testbench structure, TCL commands, and profiler analysis for incisive performance with SystemVerilog |
| Specman Performance Handbook | Performance Aware Coding for e testbenches. Advanced Command Options and Performance Tips for working with Specman. |
NOTE - To access the documents listed in the table, click a link and use your Cadence credentials to logon to the Cadence Online Support: http://support.cadence.com/ web site.
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Let us know if these documents helped you in improving the performance of your environment. If yes, then it will be good to know by how much. You will be provided with a feedback window on the top of each document view on http://support.cadence.com
Sumeet Aggarwal