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Photo Essay and Comments on DAC 2012 in San Francisco, CA
In addition to the annotated image gallery (click here or on the image), below are some long form comments on particular aspects of this year's Design Automation Conference (DAC 2012).Verification...
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DAC 2012 Best User Track Paper Review: Deploying Model Checking for Bypass...
Bypass logic verification is a common and difficult challenge for modern VLSI design that arises in the verification of CPU, GPU, and networking ASICs. Get it wrong and/or miss a bug in the bypass...
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Video: Oski Technology’s Courageous "72 hour Verification Challenge" Using...
I've seen a lot of intriguing promotions over the years, but at DAC 2012 our partners at Oski Technology tackled a truly unique challenge. To show off their formal verification prowess they took an IP...
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Video: DAC 2012 Discussion with EET's Brian Fuller on EDA and Video
Continuing our conversation on leveraging social media for EDA, at the Design Automation Conference (DAC 2012) I had the honor of interviewing again with EETimes editor Brian Fuller -- this time the...
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DAC 2012 Video: R&D Fellow Mike Stellfox on the Emerging Bottlenecks in SoC...
R&D Fellow Mike Stellfox leads a group of trailblazers inside Cadence. Specifically, Mike's group is tasked with moving our most promising prototypes and methodological theories out of their...
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Video: DAC 2012 Update on AMIQ’s DVT IDE – New RTL Design Work Flow Support
Readers of this blog and of Team Specman will recall that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting functional verification...
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DAC 2012 Video: Dr. Kerstin Eder, University of Bristol, About Her Course on...
Dr. Kerstin Eder, a Senior Lecturer in the Computer Science department at the University of Bristol, UK, teaches a course on functional verification. In this interview she outlines how the course is...
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Using Flexible Specman License Searches
Until recently, Specman used to look for its licenses in the following strict, hardcoded order: Either 1. "Incisive Specman Elite"2. "Incisive Enterprise Simulator"3. "Incisive Enterprise Verifier"Or...
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My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e...
Growing up on VHDL, moving on to Verilog and then to SystemVerilog, I eventually discovered e (IEEE 1647)Initially I thought: "What is the fuss all about?"While exploring the language during the...
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UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in...
Just after releasing the original cowbell video series I found that Ben and Jerry's had discovered a great way to combine cowbells and charity. In April of this year, they held an event for a new...
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UVM Testflow Phase Debugging- Identifying Blocking Activities
UVM Testflow debugging capabilities have been recently enhanced through the addition of more information to the output of the show domain command. In this post, we demonstrate how this information can...
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Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics”...
A little over two and a half months ago we started sounding the "cowbell" with the release of the UVM SystemVerilog Basics videos.The resonance has been strong. As there can (almost) never be too much...
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My Constraint was Ignored – Is it a Tool Bug? – Part 2
In a previous post we showed some cases of user code that can cause ignored constraints, and how to debug that code using the Gen Debugger. In this post, we shall demonstrate another important example...
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Video: DVCon 2012 Digital-Mixed Signal (DMS) Expert Neyaz Khan on UVM Mixed...
E-mail reminders for the DVCon 2013 Call For Abstracts prompted me to look through my DVCon 2012 folder -- lo and behold I came across the following video interview. It was shot during the show, but...
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Product Update: New Assertion-Based Verification IP (ABVIP) Available Now
Verifiers rejoice: R&D has just released all-new Assertion-Based Verification IP (ABVIP) code as part of Cadence's Verification IP (VIP) and SoC Catalog offerings. Specifically, the ABVIP code in...
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Video: Interview with Professional Teenage Technology Coach Kristine Bonhoff
Over the past several years at various EDA trade events, one of the more popular forums have been panel discussions and interviews asking teenagers about the technology in their daily lives. However,...
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Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈...
Ernie & Duracell"I feel great" - long pause - "I feel great, I feel great".6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great".I hear this sound coming out of my...
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SimVision Watch Window Now Accommodates Specman Watch Items
Starting from version 12.1, the SimVision Watch Window accommodates Specman watch items together with HDL watch items. Now you can use the same window to inspect all your watches. Hyperlink support in...
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A “Reflection” on Chip-Level Debugging with Specman/e and SimVision
Last week, a favorite customer of mine called me in a panic, just days from tape-out of a large multimedia SoC. After a minor change in their RTL code their Specman testbench started crashing, even...
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Report From Silicon Valley With Application Engineer Bin Ju
Luckily I was able to track down my very busy colleague Bin Ju between assignments and interview her about her first-hand observations of what's going on here in Silicon Valley today. Bin is an expert...
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