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DVCon 2012 Video: Product Engineer Chris Komar Reviews the Tutorial on Formal...
In this interview Product Engineer Chris Komar recaps the tutorial on formal apps given on Thursday March 1, 2012 at DVCon. Chris outlines how the "apps" approach can tackle verification challenges...
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Photo Essay, Video Playlist, and Comments on DVCon 2012
In addition to the annotated image gallery (click here or on the image), or the playlist of videos on some of the papers, panels, partner activities, and tutorials ((click here or on the composite...
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Video: Oski Dares You to Challenge Their Formal & Assertion-Based...
I've seen a lot of intriguing promotions over the years, but at DAC 2012 June 3-7 in San Francisco, our partners at Oski Technology are planning something truly unique. To show off their formal...
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CDNLive Silicon Valley 2012: Much More than Moore
Last week I had the pleasure of meeting dozens of customers at CDNLive! Silicon Valley, and learning from the keynotes, in-depth technical papers, and synchronistic conversations throughout the event....
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Video: PSL and SVA for SPICE – Yes, Assertion Based Verification (ABV) for...
In this video, Senior Architect in Virtuoso R&D Don O'Riordan shares some background information on his DVCon 2012 paper, "PSL/SVA Assertions In SPICE." Wait, aren't Property Specification...
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Lessons from CDNLive! India Best Paper -- Property Driven Simulation in IEV
Recently the CDNLive! India 2011 best paper award winner, "Complex IP Verification Methodology Using Property Driven Simulation in IEV," was published in TechOnline India. This is great news for the...
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Video: “Drive For Innovation” Finds It At Every Turn
With some notable exceptions, too often technology trade press reporting has been as dour as the general world news. However, to EETimes editor Brian Fuller, this negativity was at odds with the...
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Analyzing Error Reports When Specman Crashes
One of the most frustrating events while running a tool would be to experience a tool crash. In Specman you would usually see something like:*** Error: OS signal 11 (segmentation violation) received...
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My Constraint was Ignored – Is it a Tool Bug? IntelliGen Gen Debugger Can Help!
The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation problem that you might face. The most obvious and common generation problem is a contradiction, but the Gen Debugger...
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UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"
To quote an American pop culture catchphrase made famous by Saturday Night Live character Bruce Dickison, "I gotta have more cowbell!"In the world of functional verification this translates to "more...
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Video Tech Tip: Data Path Verification Using a Formal Scoreboard with...
This 6 minute video is a quick overview of our formal scoreboard app. Specifically, the video references the same AXI bridge example included with Incisive Formal Verifier (IFV) and Incisive...
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Specman’s Memory Management Orientation Guide (or “Honey – Please Take out...
Memory management is not something the Specman user is supposed to worry about. Nobody likes to make notes about allocations and freeing up memory segments when he's programming, and Specman supplies a...
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DAC 2012 Preview: Focus on Formal and ABV Events and Papers
In a few short weeks DAC 2012 will be upon us (June 3-7, 2012 in San Francisco, CA), and Team Verify and our colleagues on the Incisive Verification team will be there in force with detailed briefings,...
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The Facts: Why Accelerated VIP Is Needed for SoC Verification
On Tuesday May 15th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated...
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UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!
A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that...
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Tips on Writing Macros in Specman e Language
In this blog, I will present some tips that can be very useful when you write e macros. We will see which kind of macro we should use for our purposes, and what options we can use to better define our...
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Get Started on UVM-e with Free Introductory Video Tutorials
One of the many requests that we get from Specman/e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM-e...
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Inefficiency is Futile – Gain UVM e and SystemVerilog Verification...
In the world of Star Trek "resistance is futile" when you encounter the Borg. Fortunately, in verification we do not have to deal with the Borg. Nonetheless, our world provides plenty of challenges....
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Accellera Systems Initiative Releases UVM 1.1b for SystemVerilog
Accellera Systems Initiive released the UVM 1.1b on its website June 1 and announced it on the UVM World site here. Cadence is happy to see this latest release maintaining the APIs and backward...
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Using Event Ports (With Edge Attribute) to Define Simulator Sensitive Events...
There are two ways in e to define an event to be sensitive to a change of value in the simulator:1. Use simple_port and bind it to the HDL object. Then create an event that will be sensitive to...
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