UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

To quote an American pop culture catchphrase made famous by Saturday Night Live character Bruce Dickison, "I gotta have more cowbell!"

In the world of functional verification this translates to "more collateral!" Thererfore, we have released a set of byte-size videos about the basics of the Universal Verification Methodology (UVM) for SystemVerilog. Each video is under 5 minutes long and includes sound, so put on your headphones and get "more cowbell!"

This series is an introduction into the basic concepts, architecture and components of UVM. It features a mixture of slides and demos.

We decided to release the entire series publicly on YouTube [click here to view].

The initial batch consists of the following chapters:

1. Introducing UVM
2. Example DUT
3. UVM Environment
4. Interface UVC
5. Collector
6. Monitor
7. Sequence Item
8. Sequence
9. Driver
10. Sequencer
11. Agent
12. Agent types
13. Interface UVC environment
14. Virtual Sequencer - Sequence
15. Module UVC
16. Scoreboard
17. DUT Functional Coverage
18. Testbench
19. Test
20. Configuration
21. Factory
22. Phases
23. Objections
24. Virtual Interface

If you have UVM fever, remember the only prescription is "more cowbell!".

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer