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Improve Debug Productivity - SimVision Video Series on YouTube
Most verification customers claim that they are spending over 50% of their verification effort in debug. If so, you should check out these latest SimVision debug videos since you will quickly see how...
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DVCon 2013 for the Specmaniac
At the upcoming DVCon (in San Jose, CA February 25-28), Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here). Of course,...
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DVCon 2013 for Formal and ABV Users
At the upcoming DVCon (in San Jose, CA February 25-28), Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here). However, Team...
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Using the ‘restore -append_logs' Feature
As described in Specman Advanced Option appnote, Specman Elite supports dynamic load and reseeding. This allows the user to run the simulation up to a certain point (often until right after reset) and...
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IBM and Cadence Collaboration Improves Verification Productivity
Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through...
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It’s Coming: Udacity CS348 Functional Hardware Verification Course Launches...
On October 18, 2012 Google, NVIDIA, Microsoft, Autodesk, Cadence and Wolfram announced their collaboration with Udacity. Working with Udacity, each of the companies listed above is developing new...
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Planning to Go to DVCon 2013 Next Week? If So, Don't Miss the Debug Tutorial...
TUTORIAL: Fast Track Your UVM Debug Productivity with Simulation and AccelerationSession: 5T on Thursday, Feb. 28th from 8:30AM - 12:00PMFor more details on the debug tutorial, click hereThis debug...
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JBYOB (Just Bring Your Own Browser): Interactive Labs on Udacity CS348...
On February 19, we announced the launch date for our Udacity MOOCs course: CS348 Functional Hardware Verification, which will launch in exactly one week from now on March 12, 2013. When we communicated...
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DVCon 2013: Functional Verification Is EDA’s “Killer App”
With another year of record attendance, DVCon has again proven that a functional verification-focused mix of trade show and technical conference is what customers need to get their jobs done. Here are...
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Launch Time – Udacity CS348 Functional Hardware Verification Hits the Web...
Coinciding with the first day of CDNLive! Silicon Valley, our UdacityMOOCs course on Functional Hardware Verification will go live today! Developing this course has been a very rewarding experience and...
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Specman: Getting Source Information on Macros
When you write a define-as or define-as-computede macro, you sometimes need the replacement code to contain or to depend on the source information regarding the specific macro call, including the...
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Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software...
Great news.... Incisive Debug Analyzer (IDA) is one of five finalists for the EETimes/EDN Annual Creativity in Electronics (ACE) Awards in the Software Product of the Year category. In addition to IDA,...
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Develop for Debugability – Part 1
Debugging is the most time-critical activity of any verification engineer. Finding a bug is very often a combination of having a good hunch, experience, and the quality of testbench code that you need...
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Develop For Debugability – Part II
Looking at Coding Styles for DebugIn this blog post we are going to discuss 3 different cases where coding style can help you debug easier: 1. Declarative vs. Sequential Coding 2. Method Call...
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Mode Support for SimVision “Stop Simulation” Button
Prior to Incisive Enterprise Simulator (IES) 12.1, clicking the SimVision "Stop Simulation" button would stop the simulation both in an HDL context and in a Specman context if Specman was present in...
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New Specman Coverage Engine - Extensions Under Subtypes
This is first in a series of three blog posts that are going to present some powerful enhancements that were added to Specman 12.2 in order to ease the modeling of a multi-instance coverage...
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Introducing UVM Multi-Language Open Architecture
The new UVM Multi-Language (ML) Open Architecture (OA) posted to the new UVMWorld is the result of a collaboration between Cadence and AMD. It uniquely integrates e, SystemVerilog, SystemC, C/C+, and...
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How Can You Continue Learning About Advanced Verification at Your Desk?
How much time do you spend "playing" and "learning" before you try a new EDA tool, feature, or flow?Do you really take a training class and sift through the documentation or books about the subject...
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The Art of Modeling in e
Verification is the art of modeling complex relationships and behaviors. Effective model creation requires that the verification engineer be driven by a curiosity to explore a design's functionality,...
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Fujitsu Gets 3x Faster Regression with Incisive Simulator and Enterprise...
Verification regression consumes expensive compute resources and precious project time, so any speed-up has both a technical and business impact. As announced July 17, Fujitsu was able to improve both...
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