Clik here to view.
New Specman Coverage Engine (Part II) - Using Instance-based Coverage Options...
In the last coverage blog, we showed how the extensions of covergroups under when subtypes can help us write a reusable per-instance coverage.We described a test case where a packet generator unit can...
View ArticleClik here to view.
That Cowbell Must be Registered – Introducing the UVM SystemVerilog Register...
In May of 2012 we launched the initial cowbell YouTube video series on the basics of UVM for SystemVerilog IEEE 1800 and e IEEE 1647.This was followed by a video series on debugging with...
View ArticleClik here to view.
New Specman Coverage Engine (Part III)—Use of Extension Under "when" vs....
In both previous coverage blog posts (Part I and the Part II), we showed two solutions for refining instance-based coverage in a reusable way. And in doing so, we demonstrated a case where using the...
View ArticleClik here to view.
Configurable Specman Messaging Webinar Archive Available Now
Configurable Specman Messaging for Improved ProductivityWebinar Archive Available Now!Hello Specmaniacs:Ever wondered how to switch on all messages, or how to switch all of them off? Or get confused by...
View ArticleClik here to view.
e Macro Debugging
When creating a testbench using the MDV methodology, you want to write intelligent code whose behavior can be easily modified.Using e macros can greatly improve your productivity by raising the level...
View ArticleClik here to view.
Generic Dynamic Run-Time Operations with e Reflection, Part 1
Untyped Values and Value HoldersThe reflection API in e not only allows you to perform static queries about your code, but it also allows you to perform dynamic operations on your environment at run...
View ArticleClik here to view.
Coverage Unreachability UNR App - Rapid Adoption Kit
The Cadence Incisive Enterprise Verifier (IEV) team recently developed a self-help training kit - a Rapid Adoption Kit - to help users gain practical experience applying IEV's Coverage Unreachability...
View ArticleClik here to view.
Covering Edges (Part I) – Cool Automation
With random generation, most of the fields are due to be quite well covered. If the field is of a type with a wide space, e.g. address is of 32 bits, then most likely not each and every of the...
View ArticleClik here to view.
Test Your Units Before Your Units Test You — Testing Your Testbench
Bugs are a part of life in any complex software development project. This is no different in the testbench development world. Most bugs get discovered eventually. The question is: At which stage of the...
View ArticleClik here to view.
Practical Guide to the UVM for $15 - Virginia, There is a Santa!
Wondering what to get the verification engineer on your list? You know, the one with the zealous love of SystemVerilog and UVM? It's the Practical Guide to Adopting the UVM, Second Edition for only...
View ArticleClik here to view.
Generic dynamic run-time operations with e reflection Part II
Field access and method invocationsIn the previous blog, we explained what are untyped variables and value holders in e, and how to assign and retrieve values to/from them. In this and the next blogs,...
View ArticleClik here to view.
ADI Success Verifying SoC Reset Using X-Propagation Technology - Video
Analog Devices Inc. succeeded in both speeding up the simulation and debug productivity for verifying SoC reset. In November 2013 at CDNLive India they presented a paper detailnig the new technology...
View ArticleClik here to view.
Covering Edges (part II)—“Inverse Normal” Distribution
In the previous example, we used the "select edge" to generate edge values for fields. But in many cases, what you really want to generate is not the exact edge, but "near the edges". For example, for...
View ArticleClik here to view.
Cadence and AMD Add New UVM Multi-Language Features
0 0 1 454 2594 Cadence Design Systems 21 6 3042 14.0 Normal 0 false false false EN-US JA HE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0;...
View ArticleClik here to view.
Incisive Verification: Top 10 Things I Learned While Browsing Cadence Online...
There is always a demand, in most corners of the world today, for learning and troubleshooting something simply and quickly. Most users of any product or tool want access to a self-service knowledge...
View ArticleClik here to view.
e Language Editing with Emacs
Specman and e have been around for a while, and some clever people have developed a nice syntax highlighting package for Emacs. What does this package do? Well, have a look yourself: Editing in Emacs...
View ArticleClik here to view.
Incisive vManager at DVCon - Come See It!
Have you heard the news? There is a new version of vManager announced this week, right in time for DVCon. vManager has been completely re-architected to be a database driven environment, scaling to...
View ArticleClik here to view.
Resetting Your UVM SystemVerilog Environment in the Middle of a Test —...
In general, reset will be applied at different times within a test. 1. Reset at the beginning of a testIn a typical UVM test you might start out by applying a reset, and then go on to configure your...
View ArticleClik here to view.
New Incisive Verification App and Papers at DVCon by Marvell and TI
If you're an avid reader of Cadence press releases (and what self-respecting verification engineer isn't?), you will have noticed in our Incisive 13.2 platform announcement back on January 13th that...
View ArticleClik here to view.
Randomizing Error Locations in a 2D Array
A design team at a customer of mine started out with Specman for the first time, having dabbled with a bit of SystemVerilog. I can't reveal any details of their design, but suffice to say they had a...
View Article