The UVM Multi-Language Open Architecture open-source library was recently updated with new features. The hallmarks of this solution continue to be the ability to integrate verification components of multiple languages and methodologies at the testbench level, expanding beyond simple connectivity at the more limited data level, and the multi-vendor support.
Interestingly, multi-language is a bit of a misnomer – the critical part of the name is Open Architecture. For sure, this industry has verification IP written in multiple standard languages – SystemVerilog, SystemC, and e – but that isn’t the whole story. If language defined the verification component, then AVM, VMM, OVM, and UVM verification components would all interoperate without any modification or glue code because each one is written in the same language – SystemVerilog. However, the code needed to be organized into libraries with generally accepted methodologies to create verification components that could be easily reused. As a result, companies have created many well-verified components that need a lot of additional code to integrate into a coherent verification environment. By coherent we mean an environment with organized phases, configuration, and control despite the different libraries. When we add components from other languages, it's easy to see that simple data connections between the languages are quite necessary, but insufficient, to enable verification reuse.
The new UVM ML-OA 1.3 builds on the foundation established in June with the initial download posted on UVMWorld. The important new feature is multi-language configuration. With this new feature, users can configure integers, strings, and object values using the hierarchical paths established when the environment is constructed. Wildcards are permitted but the interpretation is the responsibility of each integrated framework. The release includes three new demos to help you become familiar with the new capability. In addition, there are several ease-of-use enhancements aimed at making it easier to set up a multi-language environment and support for g++ 4.1 and 4.4. The release notes and documentation in the 1.3 tarball have more details on the new features and how to use them.
UVM ML-OA goes beyond inter-language communication to provide the integration that allows verification components to work together in a coherent testbench. The download is open source and known to run on all major simulators.
Cadence is also working with its partners to develop a portable UVM-SC adapter that will enable running SystemC verification environments with UVM-ML-OA using the SystemC support built into the simulator. Cadence will test the adapter with the Incisive platform, and its partners will test it with the Mentor and Synopsys simulators.
So if you haven’t yet, come join the 2500 others who have downloaded UVM ML throughout its history and your verification reuse will be more productive.
=Adam Sherer, Incisive Product Manager