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Applying Software-Driven Development Techniques to Testbench Development
Over the past couple of years there has been some interest in applying a software development technique called unit testing in the hardware development flow. One of the reasons is that unit tests allow...
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Incisive Simulation and Verification: Top 10 New Things I Learned While...
In my first blog of this quarterly series, I focused on how Rapid Adoption Kits (RAKs), developed by Cadence engineers, are enabling our users to be productive and proficient with Cadence products and...
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e and SystemVerilog: The Ultimate Race
For years we've watched the e and SystemVerilog race via countless presentations, articles, and blogs. Each language is applied to SoC verification yet the differences are well documented so any...
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sync and wait Actions vs. Temporal Struct and Unit Members
Using sync on a temporal expression (TE), does not guarantee that the execution will continue whenever the TE seems to succeed. In this example, the sync action will miss every second change of...
View ArticleClik here to view.
Updates from the UVM Multi-Language (ML) Front
An updated version of the UMV-ML Open Architecture library is now available on the Accellera uploads page (you need to login in order to download any of the contributions).The main updates of version...
View ArticleClik here to view.
Implementing User-Defined Register Access Policies with vr_ad and IPXACT
The register and memory package vr_ad for Specman is used in pretty much every verification environment. In most cases today, the register specification is captured in an IPXACT description and the...
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Incisive Simulation and Verification: Top 10 New Things I Learned While...
Cadence Online Support, http://support.cadence.com, provides access to support resources including an extensive knowledge base, access to software updates for Cadence products, and the ability to...
View ArticleClik here to view.
Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More
The profiler helps to figure out the components or the code streams that take the maximum time or memory during simulation. Over the years, profiling was more inclined toward RTL and GLS than...
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Expectations Versus Reality — How I Misjudged the Apple MacBook Pro Retina...
In technology, simple concepts can have huge implications, and sometimes what you might dismiss as a minor feature, turns into a major improvement. For example, let me tell you about my experience...
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Objection Mechanism Synchronization Between SystemVerilog and e Active...
Suppose you have two verification components, each driving its own portion of the DUT (for example, two protocols driving a DUT, one implemented in e and the other in System Verilog).In this case, you...
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My First Internet of Things Device: Moving from a Manual to an Automated...
The Internet of Things (IoT) has been a buzzword for quite some time now. However, thus far it has not seen wide adoption or market penetration in the home; this, at least, has been my observation....
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Troubleshooting Incisive Errors/Warnings—nchelp/ncbrowse and Cadence Online...
I joined Cadence in July 2000 and was immediately put on a three-month training to learn and understand the simulator tools. There were formal training sessions, and I had a mentor who I could ask all...
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Transferring e "when" Subtypes to UVM SV via TLM Ports—UVM-ML OA Package
The UVM-ML OA (Universal Verification Methodology - Multi-Language - Open Architecture) package features the ability to transfer objects from one verification framework to another via multi-language...
View ArticleClik here to view.
sync and wait Actions vs. Temporal Struct and Unit Members
Using sync on a temporal expression (TE), does not guarantee that the execution will continue whenever the TE seems to succeed. In this example, the sync action will miss every second change of...
View ArticleClik here to view.
Updates from the UVM Multi-Language (ML) Front
An updated version of the UMV-ML Open Architecture library is now available on the Accellera uploads page (you need to login in order to download any of the contributions).The main updates of version...
View ArticleClik here to view.
Implementing User-Defined Register Access Policies with vr_ad and IPXACT
The register and memory package vr_ad for Specman is used in pretty much every verification environment. In most cases today, the register specification is captured in an IPXACT description and the...
View ArticleClik here to view.
Incisive Simulation and Verification: Top 10 New Things I Learned While...
Cadence Online Support, http://support.cadence.com, provides access to support resources including an extensive knowledge base, access to software updates for Cadence products, and the ability to...
View ArticleClik here to view.
Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More
The profiler helps to figure out the components or the code streams that take the maximum time or memory during simulation. Over the years, profiling was more inclined toward RTL and GLS than...
View ArticleClik here to view.
Expectations Versus Reality — How I Misjudged the Apple MacBook Pro Retina...
In technology, simple concepts can have huge implications, and sometimes what you might dismiss as a minor feature, turns into a major improvement. For example, let me tell you about my experience...
View ArticleClik here to view.
Objection Mechanism Synchronization Between SystemVerilog and e Active...
Suppose you have two verification components, each driving its own portion of the DUT (for example, two protocols driving a DUT, one implemented in e and the other in System Verilog).In this case, you...
View Article