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Blast from the Past, Take 2: Why Are We Still Designing with Verilog 2000 – A DVCon Preview

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SystemVerilog was ratified and released by the IEEE 10 years ago, in 2005. Since then, it has been rapidly adopted for verification. The reasons are simple – it is much more powerful than classic Verilog, and the language only has to be handled by a few classes of EDA tools, such as the Incisive Enterprise Simulator, for example.

However, in the electronic design space we see a much slower rate of adoption than in verification, and for good reasons. When you model your device under test (DUT) using SystemVerilog design constructs, such as interfaces and enumerated types, to name a few, you need to make sure your entire tool chain supports them, which can include: linting, simulation, equivalence checking, property checking, synthesis, emulation, acceleration, and potentially other applications. In other words, when you model using SystemVerilog, the bar is much higher, and so is the risk for adoption.

However, there are a few brave designers out there who have found ways to achieve the advantages of the new language features, while managing the risks. Those engineers are leading the way for broader-scale adoption within the industry. They have seen, and displayed, the possibilities of SystemVerilog, and they will share their experiences on Monday, March 2 at 9:00am PST in San Jose, CA at the DV Con 2015 Accellera tutorial, in a presentation titled: SystemVerilog Design: User Experience Defines Multi-Tool, Multi-Vendor Language Working Set.

At the presentation, you will hear from Junette Tan of PMC-Sierra, as well as from Mike Schaffstein of Qualcomm. In addition, you will get insight from industry veteran Stu Sutherland about how to use SystemVerilog assertions as part of the design methodology.

This is going to be very interesting and exciting. It is the real deal. The experiences related by these experts stem from the implementation of actual projects that went on to produce working silicon. 

Yours truly will be the MC, and I cannot wait to see you at the presentation in sunny California.

Axel Scherer

Twitter: @axelscherer 

 

 


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