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Pablo Picasso and the Power of Abstraction: Make Sense of Your Verification...
Abstraction is a key concept that makes it easier for humans to deal with large and complex systems. Since abstraction reduces complexity, without abstraction, hardly any innovation would be possible...
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Before There Was a Transaction, There Were Signals
Transaction-based verification has been around for many years. A transaction is an abstraction that consists of a single transfer of data and control signals. With today’s complex SoCs, we need to...
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Blast From the Past—Or Debugging HDL Race Conditions And Glitches
In 1999, the movie Blast from the Pastwas released. It begins in Los Angeles in the 1960s, during the Cold War era. In this movie, a nerdy, engineering-type father was afraid of a potential conflict...
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Heading Off the Butterfly Effect—The SimVision "Quick Diff"
Functional Verification Debug Blog - SimVision Gems Most engineers are familiar with the “Butterfly effect” – the notion that a small change can result in enormous repercussions in the future. A...
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The Apple Car: Not a Question of Ability, But a Question of Intent
Rumors have been flying for years about whether Apple will create a car. Recently, this has gained more traction due to some key hires by Apple, and by boastful comments by an Apple employee, which is...
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Blast from the Past, Take 2: Why Are We Still Designing with Verilog 2000 – A...
SystemVerilog was ratified and released by the IEEE 10 years ago, in 2005. Since then, it has been rapidly adopted for verification. The reasons are simple – it is much more powerful than classic...
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Deque to the Rescue—Introducing the e Template Library
A customer working on a VIP component identified that the performance of one of their protocol checkers, written in ‘e’, is significantly worse than the performance of the competing solutions. Profiler...
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There Will Be Blood – Ahem, Rather, Electrons If Apple Decides to Build a Car
Every modern device, even the ones with modest complexity, could never be developed by a single person at the quality, cost, and performance levels we enjoy today. This has been true for over 100 years...
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Don’t Lose Extra Simulation Cycles
After reading the rest of this blog, you might guess the truth, which is that my "designing" skills go back to the 8086 processor! In this blog, I have used a 64-bit register (Well, I could make it...
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What Does It Take To Satisfy Your Need For Verification Speed? You Gotta RAK It!
A few weeks ago I discussed how bigger is (often) better. Obviously, everyone has a need for “more cowbell” as well as a need for speed. The questions to ask are:What do you have to do to accelerate...
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In New York–Boston/Brighton–Mountain View: Modern Formal and Simulation...
Growing up in the '80s can damage your memory – particularly when it comes to bad music.At DVCon 2015 in San Jose I spoke with Michael Theobald, PhD, who is an adjunct professor at Columbia University,...
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Moore’s Law 2.0—The End and Beginning of a New Era!
April 19 marks the 50th anniversary of Moore’s law. This is not just a very significant anniversary for technology, but for all of mankind. Here is why. We have never before seen such explosive...
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Moore’s Law 2.0–How Small It Is To Be A 14nm FinFET
As I mentioned in my Blog on April 7, Moore’s law will turn 50 on April 19. What I did not emphasize enough in my discussion on silicon process evolution is size, or more accurately tininess.In that...
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Top 10 Common Questions Regarding New Cadence Indago Debug Platform
By now, you all must have read the news that Cadence has unveiled the new Indago™ Debug Platform, which boosts debugging productivity by up to 50%.What's the secret sauce between the productivity gains...
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The Time is Ripe—SystemVerilog Adoption for Design Is Gaining Momentum
On March 2, 2015, I had the privilege of moderating the Accelera tutorial at DVCon San Jose, which focused on the adoption challenges and the benefits of using SystemVerilog for design (SVD).The...
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Specman deep_copy()—Creating Too Many Structs
This blog starts with a description of a debugging session of a mysterious behavior we encountered. Unlike a good mystery book, I will tell you upfront who did it—deep_copy(). In the second part of the...
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Multi-Language Verification Environment—Getting First Run in Few Minutes
Seems that by now, every one in the industry realizes that multi-language verification environments are not a faraway vision, something only for eccentric verification experts. Multi-language is here,...
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Multi-Language Verification Environment (#2) – Passing Items on TLM Ports,...
In the previous blog post, we created a simple multi-language verification environment, running UVCs implemented in SystemVerilog and in e.The architecture of the environment is as pictured here: We...
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It’s Time to Modernize Debug Data and It’s Happening at DAC
“The leading edge is 1 million gates.” That was the news when we approved IEEE Verilog 1364-1995 and the open VCD syntax standard for debug data interoperability. Now the leading edge is over 1 billion...
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Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a...
In the previous blog post, we demonstrated connecting a checker implemented in SystemVerilog to a monitor implemented in e.In this post, we will show a fast way for adding a system-level data checker –...
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