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Multi-Language Verification Environment (#4)—Multi-Language Hierarchy
In the previous posts in this series on Multi-Language Verification Environment, we created a multi-language environment containing UVCs implemented in e and SystemVerilog. This environment is...
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Aargh!!! How Can I Read Arguments from the Command Line Without argv?
Many times a user would like to be able to modify the behavior of a program based on arguments on the command line. Let’s take as an example a user who would like to pass the name of a file which...
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Debugging Multi-Language Verification Environments
As shown in previous blog posts in the Multi-Language Verification Environment series, creating multi-language verification environments is not difficult. Using UVM-ML, we can pass data between...
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The Dark Side of Constraints on 'do-not-generate' Fields
The art of expressing hardware functionality through constraint language is often one of the trickiest parts of functional verification. Unlike procedural actions that are executed locally one by one,...
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Performance and the Use of Port mvl Lists (or, Nothing in Life is Free…)
When connecting to the DUT signals, we usually refer to the values as 0s or 1s. But sometimes there is a need to know the exact multi-value logic, or to write an mvl value (e.g., init the signal to...
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Extending the e Language with Anonymous Methods
We're happy to have guest blogger Thorsten Dworzak describe how he added anonymous methods to the vlab_util package from Verilab. So here it goes:Many programming languages like Python, Perl, and Ruby...
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Make Your Debugging Faster by Recording Your Simulator
One of the famous quotes of Brian Kernighan is: "Debugging is twice as hard as writing the code in the first place. Therefore, if you write the code as cleverly as possible, you are, by definition, not...
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Incisive vManager Free Video Training
The Incisive vManager tool for professional verification planning and management has now been officially released for almost two years. As demand for the Incisive vManager solution increases, so does...
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A Coverage Time-Saving Tip
How often has this happened to you? You are re-using a part of a previous design in your new design, you are in the depths of coverage closure, both functional and design code coverage. You discover...
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Using Tables to Handle Configurability in Incisive Enterprise Specman
Most, if not all, designs which are being verified today are configurable. This is just a fact of life, with companies trying to reuse as much IP as possible in multiple different projects, or...
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Functional Verification Closure—Are We Done Yet?
In my job as product marketing director for vManager and MDV, I get to hear this discussed all the time—when will verification be done? If not asked overtly, at a minimum it’s that rattling and...
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UVM-ML OA: Now Within Incisive Platform As Well!
Open-source software has many advantages. In short: you can see it (the code), you can inspect it (check out what Coverity revealed in the Android kernel), and you can change it. But the fact that...
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e Templates – Cool Tool, Now Even Cooler
One of the reasons why verification engineers love e is the power it gives them as no other language can. The combination of macros,reflection and extension allows you to create high quality utilities...
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How to Handle a Binding Catastrophe
Are you busy debugging your environment topology and coming up against components getting unexpected data? Have you found yourself asking “who is passing data to this monitor, and why?”?Components in...
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Modelling a Value Holder Template with the Value “new-ed” by Default
In many companies, there is a well-defined flow for handling monitored data items: match the input data to output data (or, match a response to a request), update data, for example latency or the time...
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RTL Signoff vs. Functional Signoff
The notion of signoff has many layers to it, both in terms of complexity but also in terms of meaning. In my last blog post, I talked about some of the imprecise attributes of functional verification,...
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Building Efficient Scoreboards
A “scoreboard” is a verification component that checks the data sent to the DUT against the data received from the DUT. The fundamental flow of the scoreboard is simple:Items sent to the DUT are added...
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Simulation Acceleration—Maximizing Simulator Performance
"Simulation Acceleration” or “Accelerated Verification” are terms commonly used to describe a verification environment in which the Device Under Test is synthesized and runs on the emulator, while...
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How to Find Where Declared e Entities Are Used
The e Reflection API allows you to perform various queries on entities in your own code, and to figure out which types, fields, methods, and so on have been declared in the code, the relations between...
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Why Do We Need a Verification Language?
This month, we celebrate the 20th anniversary of Specman’s introduction to the public—at DAC 1996 in Las Vegas. This introduction was not simply of a new tool—it was the introduction of a new concept....
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