Multi-Language Verification Environment (#2) – Passing Items on TLM Ports, Using UVM ML

In the previous blog post, we created a simple multi-language verification environment, running UVCs implemented in SystemVerilog and in e.

The architecture of the environment is as pictured here:

We will now add to this environment a system-level checker, implemented in SystemVerilog.

A standard recommended way for passing items is via TLM ports. For connecting ports instantiated within components implemented in different languages, we use UVM-ML.

1. If you haven’t already, download and install UVM-ML from Accelera UVMWrold
2. When compiling the environment, use the required UVM_ML flags. The best way for adding the required flags is using the option files that are provided within the UVM-ML library.

For example, running an environment containing e and SystemVerilog UVCs:

irun ./test.sv \

 -f ${UVM_ML_HOME}/ml/run_utils/ml_options.32.f \ 

 -f ${UVM_ML_HOME}/ml/run-utils/sv_options.32.f \

 -f ${UVM_ML_HOME}/ml/run_utils/e_options.32.f \     

 -uvmtop SV:svtest -uvmtop e:./top.e \

 -exit 

See the UVM-ML User Guide, residing under the docs directory in the UVM-ML library, for the detailed description of compiling multi-language environments. 

Passing structs via the TLM ports is achieved by serializing the transaction content, sending it to the connected port, and de-serializing it there. This process requires two things:

1. Need to know which type mapped to which type in the other language (known as “type mapping”)
2. The serialization and de-serialization need to match, in order to get the same transaction on each side

For connecting the e monitor to the SystemVerilog checker using the standard TLM analysis interface, we have to define the required type in SystemVerilog – a struct matching the xserial_frame struct - and implement the serialization and de-serialization. The fastest way to do so is using IES mltypemap stand-alone utility. We provide to it as an input the e code containing the definition of the e struct, and it creates e and SystemVerilog files, containing the corresponding SystemVerilog definition and all the code that is required for passing the struct between e and SystemVerilog.

For example, if this is the definition of the e struct:

Running on it mltypemap will result with this definition in SystemVerilog:

Note how mltypemap defines all the required types,  xserial_frame_format_t in this example. 

Now that we have a SystemVerilog definition of xserial_frame, we can implement the checker comparing the monitored xserial_frames to the monitored ubus_transfers. All that’s left is to connect the ports of the monitors to the checker’s ports. The connection can be implemented either in SystemVerilog or in e, in this example – we do this in SystemVerilog, using uvm_ml::connect(). Before connecting ports of different languages, the ports have to be registered to UVM-ML. SystemVerilog ports are registered using UVM-ML TLM register(), and e ports should be bound to external.

Connecting the SystemVerilog checker to the e monitor:

SystemVerilog:

1. Register the checker’s port to UVM-ML
2. Connect the ports, using uvm_ml:connect()

e:

1. Bind the monitor’s port to external

That’s it! The e monitor and the SystemVerilog checker are now connected. When the monitor writes frames on the port, the checker will get them.

As you can see, the amount of code required for passing data from e to SystemVerilog is quite small:

1. Match the types and implement the serialization
   1. mltypemap automates this task
   2. Register the SystemVerilog port to UVM-ML
   3. Bind the e port to external
   4. Connect the ports, either in e or in SystemVerilog, using UVM-ML connect_names() or connect()
      

You can see a detailed description and examples of passing items via TLM ports in UVM-ML examples, User Guide, and Reference Manual.

For mltypemap, see Specman documentation on Cadence Help.

The next blog post in this series, Multi-Language Verification Environment – Connecting UVM Scoreboard to a Multi-Language Environment, will show a simple way of adding a system-level checker to the environment using UVM e Scoreboard. This scoreboard uses TLM ports as its API, so it can connect to models and checkers implemented in one of the languages – e, SystemVerilog, or SystemC.

Happy verification,

Efrat Shneydor