On March 2, 2015, I had the privilege of moderating the Accelera tutorial at DVCon San Jose, which focused on the adoption challenges and the benefits of using SystemVerilog for design (SVD).
The consensus was that, although it has been 10 years since the ratification of IEEE 1800, we are finally seeing momentum in the adoption of language features that are extremely beneficial for modeling designs. In the verification arena, many features have been adopted quickly for two reasons: the productivity gap was very high and the adoption challenges were lower. However, in the design space, the adoption challenges are much higher. This is because a much larger set of tool types and vendor implementations must consistently support the same subset of the language in order to work productively.
In the tutorial, we heard from Stu Sutherland of Sutherland HDL, who talked about the use of SystemVerilog assertions (SVA) in the design space.
Junette Tan followed up by describing how PMC Sierra mounted a concerted effort, starting in 2010, to adopt SystemVerilog for design. She explained the challenges and the gains the company made by being an SVD pioneer. We captured a short video with Junette to summarize her talk.
(Please visit the site to view this video)
Then followed Mike Schaffstein, who illustrated the methodology he deployed to pilot SV for design at Qualcomm. He discussed the methodology and the SV constructs that work, and where the remaining challenges lie. Mike spoke in the video below about his experience.
(Please visit the site to view this video)
Finally there was a panel discussion that also allowed the audience to ask more questions. Overall, this session was very well attended, and as far as I know, it was the most heavily attended session at DVCon this year. As a benefit, the discussion and audience interaction was very lively. My thoughts on this tutorial are summarized in this video.
(Please visit the site to view this video)
The subsequent DVCon survey results showed that the vast majority of the attendees were inspired and excited by the tutorial, and many expressed their intent to start adoption of SystemVerilog for design in 2015.
Axel Scherer, Chief Tech Adoption Guy
Twitter: @axelscherer