On October 24, Cadence and Arm announced early access to the Xcelium Parallel Logic Simulation on Arm-based servers. It was demonstrated running on Cavium ThunderX2 and Qualcomm Centriq servers at the Arm Techcon event on October 25 and 26. This represents a new development in low power, yet high performance simulation solutions for the EDA industry.
Ensuring that designs function correctly is a huge challenge for the electronics industry—it can account for 70% of the entire industry’s computing workload. Growth in this area, and a reduction in the amount of computing power required for verification, is paramount for the continued improvement of the next generation of chips.
Here’s what the partnership between Arm and Cadence adds to this area: The Xcelium simulator runs natively on Arm-based servers! This allows for huge power and capacity benefits when executing both high-throughput and long latency workloads. Both Cavium and Qualcomm introduced Xcelium in their Arm Techcon presentations.
Xcelium Simulator—part of the larger Cadence Verification Suite—speeds-up single-core tasks, and boosts multi-core tasks 3-10X. Utilizing Xcelium lets companies run workloads on the best core configurations for their verification tasks. Beyond that, Xcelium also automates the compile and elaboration design and verification testbench code to keep execution speedy on multi-core servers.
“Collaborating with Cadence on the Xcelium simulator is a key milestone in accelerating the electronic design ecosystem for Arm-based servers,” said Drew Henry, senior vice president and general manager for Arm’s Infrastructure Business Unit. “The flexibility of the Arm architecture will create new opportunities for more compute core density for EDA workloads, enabling high-performance parallel simulation while reducing the power and floor space required for implementing and validating silicon designs.”
For the formal announcement, check here.
For more information about other Arm-based Cadence solutions, check here.