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Single Core vs. Multi Core: Simulation in Stereo
Latency simulations are the sworn enemy of the verification schedule. A handful of tests add days to weeks for each regression cycle; and when you add in the fact that they can’t be parallelized like...
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Teradyne "Formally" Adopts JasperGold FPV
CDNLive Boston 2017: Teradyne reveals their success with JasperGold in their presentation, Success using Formal Verification--and now they join the ever-growing fold of JasperGold FPV (Formal Property...
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Teradyne Standardizes on Xcelium Simulator
Today, Cadence announced that Teradyne has adopted the Xcelium™ Parallel Simulator for use in ASIC development. They’ve reached a 2x speedup with Xcelium when compared to their old simulation...
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Munich October 18—Come See SystemC Evolution Day!
Sorry, you missed Oktoberfest (which is mostly in September anyway). But come to Munich in October for SystemC Evolution Day—a workshop on the evolution of SystemC standards held in Munich, Germany on...
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Cadence and Arm Announce Early Access to Xcelium Parallel Logic Simulators on...
On October 24, Cadence and Arm announced early access to the Xcelium Parallel Logic Simulation on Arm-based servers. It was demonstrated running on Cavium ThunderX2 and Qualcomm Centriq servers at the...
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Adding Annotations in Your e Code
If you have had a chance to work with languages like Java or C#, you might have come across Annotations. Since the Specman 17.10 version, annotations have become part of the e language! (See Java...
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Slaying the Gate-Level Simulation (GLS) Dragon: Your Knight Is Here!
Even today, gate-level simulation is still a major signoff step for most semiconductor projects. However, those simulations can take days or weeks to run. A bug that causes a rerun of a gate regression...
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X-Propagation: Xcelium Simulator’s X-prop Technology Ensures Deterministic Reset
All chips need to cold reset on every power-up. Warm resets, however, are a bit more complicated. Take a smartphone screen, for example. The screen may power down while the phone is idle. However, the...
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Slaying the Gate-Level Simulation (GLS) Dragon: Your Knight Is Here!
Even today, gate-level simulation is still a major signoff step for most semiconductor projects. However, those simulations can take days or weeks to run. A bug that causes a rerun of a gate regression...
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26262 4U: Infineon and the Incisive Functional Safety Simulator
Infineon and Cadence have a bit of a history: they’ve been working together on functional safety mechanisms for around two and a half years now, and Infineon has been using the entire Cadence...
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Check Again: Cadence Announces Release of the First PCIe 5.0 VIP—With...
On November 28, 2017, Cadence announced the release of the first available PCIe® 5.0 Verification IP. This new VIP gives designers access to Cadence’s TripleCheck technology—which gives designers a...
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ROHM CO., Ltd Adopts Our Functional Safety Verification Solution
On July 17, 2017, Cadence announced that the Cadence® Functional Safety Verification Solution had been adopted by ROHM CO., Ltd as part of its deisgn flow for ISO 26262-compliant ICs and LSIs for the...
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Moving to Xcelium Simulation? I’m Glad You Asked
Ready to take the next step in simulation technology with a true third-generation engine, with multi-core technology? Cadence® Xcelium™ Simulator allows you to have unprecedented control over your...
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X-Propagation: Xcelium Simulator’s X-prop Technology Ensures Deterministic Reset
All chips need to cold reset on every power-up. Warm resets, however, are a bit more complicated. Take a smartphone screen, for example. The screen may power down while the phone is idle. However, the...
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Infineon’s Coverage-Driven Distribution: Shortcutting the MDV Loop
There are more ways to improve productivity in the verification process than simply making the simulation run faster. One of these is to cut down on the amount of time engineers spend working hands-on...
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Save & Restore with More: Preserve Your Entire SoC
The concept of Save and Restore is simple: instead of re-initializing your simulation every time you want to run a test, only initialize it once. Then you can save the simulation as a “snapshot” and...
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Register for the UVM Register Layer Webinar on January 12!
On Friday, January 12, Doulos is hosting a UVM Register Layer webinar, with the aim of helping users model UVM in certain less-intuitive ways. This webinar will cover the usage of user-defined front...
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App Note Spotlight - Introduction to Connect Modules
Welcome to the App Note Spotlight—a bi-weekly series where the XTeam highlights an app note that contains valuable information you may not be aware of. Today, we're going to look at connect...
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User Extensions to DUT Error
A question was raised to stackoverflow about how can one extend the dut_error() for printing more information. The capability to provide the test runners and debuggers more information upon an error...
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CRAFTing Your Aero/Defense UVM Testbench the Easy Way
So you want to build an automated testbench for your aero/defense project, eh? Luckily, there’s a solution for you. A project called CRAFT (which stands for Circuit Realization At...
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