All chips need to cold reset on every power-up. Warm resets, however, are a bit more complicated. Take a smartphone screen, for example. The screen may power down while the phone is idle. However, the user will want it to return to their pre-set brightness level on power-up. Chips have to be tested for multiple warm-reset scenarios, and each of these tests take a very long time.
Enter Xcelium Simulator, and X-propagation. Also known as X-Prop, this idea represents how X states in gate-level logic can propagate and get stuck in a system during cold or warm resets. Unresolved X states spreading through a system can cause a non-deterministic reset, which makes a chip run inconsistently at best or fail to reset at worst.
Thanks to Xcelium Simulator and X-prop technology, we can debug X issues faster—10X faster than we could if the debug was completed during GLS. Right now, GLS happens towards the end of product development, which can lead to costly fixes when bugs are found so late. GLS needs to occur no matter what, but if X is propagated through RTL simulations, then this process can be completed far earlier, allowing bugs to be caught and dealt with efficiently.
X-prop analysis can be executed in either Compute As Ternary (CAT) mode, where X is propagated exactly as it would be in hardware, and Forward Only X (FOX) mode, where X is propagated disregarding inputs. This is required due to the fact that the propagation of Xs is not properly modeled to function like hardware in RTL for Verilog and VHDL. In addition, it’s much easier to debug in RTL—doing the propagation analysis at a higher level of design abstraction—and it has a smaller memory footprint shorter run time than GLS.
Figure 1: FOX and CAT mode
Many projects fail to run these diagnostics in application-realistic ways, such as reset validation and power-down/power-up sequences, due to the time required to run these long gate level simulations. If the diagnostic is run at RTL in accordance with the standards, then the X can be propagated forward more often than it would in practice, and this is called X-optimism.
What does this mean? X-propagation through RTL enables a more complete set of reset tests to be run instead of only the essential ones. If the X-propagation tests are left to be done during the GLS stage, then it is not time-feasible to run them all. By completing all of those tests earlier, it adds a level of security in knowing that all logic gates have been tested, and 100% of the chip works, instead of simply enough to ensure standard functionality. It’s easy to use—no complicated setup required. The sequential nature of the testing lets smaller chips be used, as RTL works with non-resettable flops. Finally—and most notably—RTL is faster, and more chips verified means more chips sold.
Nowadays, X-prop technology is built into Xcelium Simulator. Xcelium X-prop technology supports both SystemVerilog and VHDL, and doesn’t require any changes to existing HDL designs. Xcelium uses the aforementioned FOX mode and CAT mode to test for X-propagation, and both of these modes show the non-LRM compliant behavior needed to run your reset verification at RTL and improve your overall chip quality.
For more information, see the RAK at Cadence Online Support.