Today, Cadence announced that Teradyne has adopted the Xcelium™ Parallel Simulator for use in ASIC development. They’ve reached a 2x speedup with Xcelium when compared to their old simulation solution.
Xcelium has quickly become a key part of Teradyne’s verification environment, providing an easy-to-use, yet very powerful, tool that runs fast and ensures high-quality designs. Beyond Xcelium, Teradyne is also using the Cadence JasperGold® Formal Verification Platform for their formal verification needs, and the Cadence vManager™ Metric-Driven Signoff Platform to comprehensively integrate all of their Cadence verification tools together.
“Rapid development and verification of our automation test equipment solutions is critical to our success,” said Andre Hendarman, Director of Mixed Signal ASIC Development at Teradyne, Inc. “The Xcelium Parallel Logic Simulator has provided us with the fastest simulation performance by far, which is helping us speed up the delivery of our test products, while also ensuring our designs are of the highest quality.”
The Xcelium Simulator supports Cadence’s System Design Enablement strategy, which enables system and semiconductor companies to more efficiently create comprehensive and clearly differentiated products more quickly.
To read the full press release, click here.