The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4(Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In ‘What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.
Amongst many new features and changes in PCIe 6.0, we will talk about one major significant new feature: L0p. The following mainly touches upon challenges and corresponding solutions based on our design and verification experiences. For more relevant PCIe 6.0 verification challenges, see Unraveling PCIe 6.0 FLIT Mode Challenges and Unraveling PCIe 6.0 Training Sequences Update and Verification Challenges.
L0p in PCIe 6.0
With the increase of demand for power consumption scaling with bandwidth usage without impacting traffic flow, the new L0p state is introduced in PCIe 6.0. Meanwhile, L0s is not supported in FLIT mode (L0s is less robust and less effective and does not support retimes, etc.). L0p is optional for link width resizing and is used in FLIT mode only.
The existing dynamic link width change can change the link, but it will lose several microseconds to do the state transition. L0p is symmetric in terms of the same width in both directions. It maintains at least one active lane during the width change to ensure uninterrupted traffic flow.
Spec introduced the negotiation details about how to enable L0p from Configuration.Complete state along with FLIT mode with TS2 exchange. Once both sides support it, how to request down or up link size, how to ack or reject, and the detailed handshake mechanism are explained in Chapter 4.2.6.7. Moreover, the new mechanism uses a new Link Management DLLP to carry the expected value.
Below are the verification challenges for L0p mode:
- Spec introduced the negotiation details about how to enable L0p from Configuration.Complete state along with FLIT mode with TS2 exchange. It is used with FLIT mode only, so we also need to consider backward compatibility to all lower speeds.
- According to the Spec, L0p width transition can be initiated by either side, and the link partner needs to either ACK or NAK in 4 us in 8b/10b mode and 1us in the other modes. The negotiation is done by using Link Management DLLP with new DLLP fields defined, such as link management type, L0p command (Request, ACK, NAK), L0p priority, link width, and response payload. All the combinations and rules need to be covered.
- During the width change, Spec defined the sequence of OS for downsizing and upsizing. For the downsizing, the lanes turned off will send an EIOSQ on the next SKP interval and then go to electrical idle. The active lanes remain to send SKP and FLITs. For the upsizing, while the data stream continues the active lanes, the lanes to be activated will follow the EIEOS rule if the data rate is Gen2 or above, followed by TS1/TS2. After the TS2 exchange, the ports send SDS followed by Control SKP. Then, eventually, data stream on all lanes. The challenge is not only implementing the logic to handle up/down-sizing but also handling different scenarios on different lanes, besides implementing checkers on Pre-lane based scenarios.
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- Like link dynamic up/down configuration in previous versions, we need to verify all the valid up/down-sizing combinations in L0p or invalid requests through error injection test cases.
In summary, PCIe 6.0 is a complex protocol with many verification challenges. You must understand many new Spec changes and think about the robust verification plan for the new features and backward compatible tests impacted by new features. Cadence’s PCIe 6.0 Verification IP is fully compliant with the latest PCIe Express 6.0 specifications and provides an effective and efficient way to verify the components interfacing with the PCIe 6.0 interface. Cadence VIP for PCIe 6.0 provides exhaustive verification of PCIe-based IP and SoCs, and we are working with Early Adopter customers to speed up every verification stage.
More Information:
- For more info on how Cadence PCIe Verification IP and TripleCheck VIP enable users to confidently verify PCIe 6.0, see our VIP for PCI Express, VIP for Compute Express Link and TripleCheck for PCI Express
- See the PCI-SIG website for more details on PCIe in general and the different PCI standards.