In case you missed any of the 5 free webinars Team Verify presented in 2011, you're in luck: all of them have been recorded and posted for you to review at your leisure. Take your pick from the following - or pop a bucket of popcorn and a family sized bag of chips and watch them all at once!
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How to Completely Eliminate SoC Connectivity Bugs - Really!
http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=516
Bugs from incorrect connectivity -- whether they're misconnected IP blocks inside an SoC or erroneous muxing of pad rings -- can kill a chip just easily as more sophisticated functional bugs. With internal connection points surpassing hundreds of thousands of nodes, the traditional approach of assigning detail-oriented summer interns to spot-check connectivity with dynamic simulations is rapidly losing effectiveness. How do you ensure that two versions of your design are equivalent (e.g., the design before power techniques and after)?
In this technical webinar, we'll show you how to apply formal verification technology to exhaustively prove with 100% mathematical certainty that all of your SoC's internal and external pad ring connections are completely correct. An included demonstration (recorded live) reinforces the concepts presented.
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Verification 1-2-3 with Assertion-Driven Simulation
http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=518
This is it: a simple, straightforward methodology that increases bug detection and produces much cleaner RTL. Totally revolutionary "assertion-driven simulation" leverages easy constraint and assertion properties to simulate, visualize, and debug your design -- plus drive coverage collection.
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Automate Assertion Generation for Simulation, Formal and Emulation Flows
http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=557
Assertion-based verification (ABV) helps design and verification teams using simulation, formal analysis, and emulation methodologies accelerate verification signoff by enhancing the RTL and test specifications to include assertions and functional coverage properties, which are logic statements that define the intended behavior of signals in the design.
The emergence of "assertion synthesis" allows for true proliferation of ABV by automating the often painful manual process of creating meaningful white-box assertions and functional coverage properties with sufficient capacity to handle complex SoC designs. Without writing any additional code, stimulus generation and additional tests will find additional bugs and improve functional coverage, integrating into your metric-driven verification (MDV) flow.
In this webinar, Cadence and NextOp Software show how assertion synthesis enables a progressive, targeted verification process, allowing design and verification teams to more easily uncover corner-case bugs, expose functional coverage holes, and increase verification observability. The included demonstration (recorded live) reinforces the concepts presented during the session.
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Quickly Find Data Transport Bugs with Formal Scoreboarding
http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=560
"Scoreboards" have been used in advanced simulation testbench environments for years. In this webinar we will show how this same concept can be implemented with formal verification tools. Consequently, you will see how to benefit from powerful formal analysis algorithms to automatically test data integrity and root out the spectrum of simple problems to extreme corner cases.
The formal scoreboarding methodology is flexible and extendable such that it can be applied to various data transport blocks including bridges, switches, routers, matrices, memory controllers, DMA controllers, and buffers. Its value to the user is a significant reduction in simulation runtime and the ability to find bugs faster with less effort. This is an exciting topic for anyone in the functional verification space.
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Simplifying Code Coverage Analysis: Automatically Separating the Wheat from the Chaff
http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=562
Code coverage is a popular methodology let alone a signoff criterion for many companies. Unfortunately, code coverage can produce an enormous number of objects, where analysis of even a small number of coverage holes can be very tedious and time consuming. Of course, completely ignoring those holes can introduce risk that might not be acceptable.
In this webinar, we show how new automation and a revolutionary "case-splitting" methodology can help you separate the wheat from the chaff -- the "reachable" versus the "unreachable" code coverage holes. While formal analysis engines (and the mathematical certainty they offer) are used under the hood, perhaps the best part of the new case-splitting approach is that the flow does not require any understanding of formal analysis and is accessible to anyone familiar with simulation. This is an exciting topic for anyone in the functional verification space. The included demonstration (recorded live) reinforces the concepts presented in the lecture portion of the presentation.
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Happy learning and Happy New Year!
Team Verify
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