The automotive world is conquering new technological heights, piggybacking on advanced semiconductor components. A typical vehicle has around 1,400 semiconductor components, and the numbers are expected to go higher as vehicles become more intelligent and autonomous. The ecosystem change in the automotive world has mutated the demand patterns for automotive chips, resulting in the growing demand for purpose-driven applications. Semiconductor components and controllers aid advanced automotive functionalities, which are more complex than consumer electronics. They are expected to work in stringent operating conditions, handling multiple operations per second with low latency. These dynamic and enhanced requirements increase chip complexity, complicating the design, development, and verification methods and making it challenging for automotive suppliers.
Renesas Electronics Corporation is a Japanese semiconductor provider and a global leader in microcontroller units (MCUs). Renesas offers MCU, system-on-chip (SoC), analog, and power products for many market segments, including automotive, industrial, and IoT. With the accelerated rise of automotive technologies, the Renesas SoC also grows in complexity, requiring increased validation efforts. As automotive chips have grown in complexity with miniaturization and advanced functionality, the safety standards have become more stringent, resulting in increased person-hours for in-vehicle semiconductor component verification. Simultaneously, the pressure to reduce time to market and design cycle duration is immense. This causes issues in the efficiency of verification progress confirmation, verification execution, and verification result confirmation.
The Challenges and Solutions
Despite following a continuous improvement methodology for developing performance verification environments and analyzing the results, Renesas found it highly time-consuming to identify performance issues and validate performance requirements. They spent more person-hours manually developing performance and functional verification environments and analyzing the results. Renesas was looking for a shorter turnaround time with limited resources while maintaining its high-quality standards.
A shorter verification process without compromising quality standards, time, and cost has become critical in product development. Renesas teamed up with Cadence to improve verification efficiency and visualize verification status using Cadence® vManager Verification Management (now Cadence®Verisium TM Manager).
Reducing Management Cost and Debug Cycle Time
Regression is one of the critical phases in increasing the design time of projects. However, when designers and management teams spend more time manually collecting and analyzing coverage results, managing and reporting coverage results costs time and money.
Delay in managing and reporting coverage results
Renesas uses Verification Management System (VMS), a management tool, to view verification results. It is a web application based on the Verisium Manager API. VMS is used to browse regression results over an HTTP browser to collect results from servers in both Vietnam and Japan.
Renesas’s old flow was time-consuming, as the results were shown only to the project managers. Designers had to send the request to collect the coverage, merge and analyze it, and then report the coverage and simulation results. There was no consistency in the simulation and coverage results. Only the simulation result (PASS/FAIL) was collected in this flow into Verisium Manager. This manual collection and analysis of coverage results was very time and resource consuming.
To resolve this issue, they created an updated flow where the simulation results and coverage are automatically collected and visualized in VMS to help reduce management time. Verisium Manager collects the simulation result (PASS/FAIL) and the coverage databases. Verisium Manager features, such as collecting coverage results and auto-merge of coverage, helped reduce management time by receiving consistent results between simulation and coverage and removing the following:
- Request to collect coverage step
- Manage merge coverage
- Manual report coverage results
Renesas reduced management coverage by 90% and total coverage management by 45%.
Delay in re-running failed cases
Renesas designers spent much time monitoring job status, analyzing, and manually re-running failed tests. The gap between manually analyzing failures and the time between midnight and the next working day was wasted and had overheads for CPU resources and disk space.
With the Verisium Manager Auto Rerun Routine feature, the Renesas team could launch and re-run failed tests and manage failure scenarios. Verisium Manager manages the re-run of failed tests following the first failure name and the failure descriptions. Combined with the failure triage feature, the Auto Rerun feature re-runs with dedicated debug options for each failure category. This helped the Renesas team save time.
With the Auto Rerun feature, designers observed a 30% reduction in overhead CPU resources and improved disk space by increasing failure categories.
The Auto Rerun feature reduced analysis work by 20% without additional CPU resources and disk space.
In regression management, Auto Rerun reduced 10% for analysis failure causes and manually re-run it.
The reduction percentage will increase with increasing failure categories.
Summary
Cadence Verisium Manager helped Renesas accelerate its performance verification. Using Verisium Manager, Renesas could reduce approximately 10.5% of the workload from the old flow. Renesas achieved this using Verisium Manager features such as collecting coverage results, auto-merge coverage, and implementing failure detection and auto re-run.
Renesas reduced 45% for coverage, 5% for issue reports, and 10% for regression. The total reduction is 10.5%
With the Verisium Manager platform, Renesas could reach 100% combined coverage, enabling them to achieve complete verification signoff. Verisium Manager helped them revamp their old verification flows and contributed to time and cost reduction.
The Future
Renesas plans to upgrade the current Verisium Manager servers into High Availability (HA) mode to centralize regression results at their Vietnam and Japan sites and utilize ML technology for failure triage tasks using the AutoTriage feature. It is also considering the integration of the Verisium Debug Analyzer and Verisium Manager for reducing debug turnaround time.
Renesas wants to work with Cadence on high-availability migration to manage regression results on a single server. Renesas also intends to reduce debugging turnaround time and improve bug detection time using the ML technology of AutoTriage. The Cadence team looks forward to working with the Renesas team on these exciting new features.
The Cadence Verisium Manager is a robust, scalable, automated verification planning and management for pre- and post-silicon functional verification. It supports multi-user, multi-engine, multi-projects, and multi-sites simultaneously.