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USB4 Version 2.0 – Next frontier in High-Speed Data Tunneling
USB4 Version 2.0 specification was recently released by the USB Promoter Group. This specification enables up to 80 Gbps link speed per direction in symmetric mode, and up to 120 Gbps link speed in...
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Demystifying PCIe Lane Margining Technology
Lane Margining which was introduced in PCIe 4.0 and has been a very important technology since then. With the doubling of the bandwidth from 8 GT/s to 16 GT/s per Lane in formulating the PCIe 4.0...
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DisplayPort (DP) Tunneling over USB4
USB4 is an industry standard that tunnels three different protocol specifications (PCIe, USB3 and DisplayPort) serially to a destination. DisplayPort (DP) tunneling over USB4 means DP protocol packets...
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CXL Enumeration: How Are Devices Discovered in System Fabric?
PCIe designed system fabrics rely on software enumeration by Operating System (OS) for device discovery. CXL 2.0 device is exposed as PCIe native endpoint and CXL 1.1 is exposed as root complex...
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PCIe Lane Margining - What changed from Gen4 to Gen6?
With new PCIe 6.0 Base specifications rolled out, the move from NRZ (non-return-to-zero) to PAM4 (4-Level Pulse Amplitude Modulation) is no surprise. To address the Nyquist frequency issues at 64GT/s,...
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How Renesas Reduced Automotive SoC Verification Time
The automotive world is conquering new technological heights, piggybacking on advanced semiconductor components. A typical vehicle has around 1,400 semiconductor components, and the numbers are...
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How to Verify Complex PIPE Interface Based PHY Designs?
High-end SOC architectures today requiring more area and higher speed to transfer and process data. To fulfill this requirement, protocol such as PCIe, USB, DP, SATA and USB4 are regularly being...
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Understanding Latency versus Throughput
One of the effects of adopting a High Level Synthesis design methodology is that the barrier between "Systems designers" and "Hardware designers" is substantially reduced if not totally eliminated....
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Training Insights – Webinar – Automating Bug Tracking with Verisium Debug and...
Join Cadence Training and Principal Application Engineer Daniel Bayerfor this free technical training webinar.The Verisium Debug Platform is optimized for scalability, supporting debugging of...
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Training Insights - Brand New Free Online Course on Perspec System Verifier...
Cadence® Perspec System Verifier is a portable stimulus, system-on-chip (SoC) verification solution. The Perspec System Verifier improves SoC quality and saves time by reducing development effort for...
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SD Host Controller for SD Card Verification
SD Host Controller was introduced to transfer data to SD Card from system memory and vice versa. It also is the standard controller to manage the SD Card (SD Memory and SDIO). SD Association (SDA)...
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Demonstrating PCIe 6.0 Equalization Procedure
The Link equalization procedure enables components to adjust the Transmitter and the Receiver setup of each Lane to improve the signal quality and meet the requirements, when operating at 8.0 GT/s and...
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Training Insights – VHDL Language and Application
Cadence has released a new onlineVHDL training course free for Cadence Customers. It is an in-depth, comprehensive course covering basic concepts, methodology, RTL coding, verification, reuse, and best...
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Introduction to Embedded DisplayPort (eDP) version 1.5
Embedded DisplayPort 1.5 (eDP 1.5) is an interface standard that is based on the DP 2.0 (DP standard), and it is designed to transport video between the system host, i.e., GPU, and device, i.e.,...
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UCIe: Enabling the Chiplet-Based Ecosystem
Universal Chiplet Interconnect Express (UCIe) is a novel specification that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at...
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DDR5 DIMM Design and Verification Considerations
DDR5 is the latest generation of the DDR server memory capable of supporting data rates of up to 8800 Mbps which is quite a leap over previous generations of DDR memories. It is used in a wide variety...
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USB3 Gen T Tunneling Over USB4
USB Promoter Group recently released USB4 Version 2.0 and this updated specification extends USB4 speed and data protocol performance, enabling manufacturers to develop products that can deliver up to...
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Automating Data Coherency and Performance Testing of High-Speed SoCs with CXL...
2023 is here, and technology trends around Compute Express Link (CXL) and the next generation of AMBA protocols (CHI-E/F) are getting more traction. The biggest challenge of today is the complexity of...
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Improve Regression Throughput and Find Bugs at Pace
Scaling chip size and increasing functionality over SoCs has increased complexity and verification time. Verification teams are concerned about the bugs that may have slipped to silicon earlier and...
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What Makes a Next-Generation Debug Solution?
For the past few decades, design and verification technology have made great progress. More sophisticated designs are verified with faster simulation and emulation. However, the debug is pretty much...
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