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Flex Ethernet (FlexE): Unlocking the Physical Bandwidth Constraints
Efficient and flexible use of bandwidth is the key to optimizingtraffic flow for any communication channel, and so for Ethernet. FlexE (Flex Ethernet) is a standard developed by the Optical...
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Training Insights – Webinar –: Solve Tricky SVA Problems with Jasper...
Are you experienced in using SVA?It’s been around for a long time, and it’s tempting to think there’s nothing new to learn. Have you ever come across situations where SVA can’t solve what appears to be...
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Cadence Unified AI/ML Solution Helps Renesas Accelerate its Verification...
With the surge in usage requirements and increasing customer demands, hardware design is quickly becoming more complex. The rapid change in market trends, with a greater focus on technologies such as...
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Accelerating Your Overall HW/SW Verification and Validation Productivity...
With the increasing complexity of system-on-chip (SoC), the associated software stack is now integral to the system’s functionality. The software stack impacts the development cost and schedules for...
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Cadence Introduces Industry’s First GDDR7 Verification Solution
GDDR7 Introduction JEDEC announced the successor to GDDR6 with many new features and a big leap in terms of operating speed. GDDR7 is a high-speed synchronous graphic DRAM with a semi-independent row...
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Understanding UCIe Design Verification Topologies
UCIe or Unified Chiplet Interconnect Express is the fastest growing chiplet interconnect standard that enables a future where a catalog of chiplets will be available to mix and match based on the chip...
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SD Host Controller for SD Card Verification
SD Host Controller was introduced to transfer data to SD Card from system memory and vice versa. It also is the standard controller to manage the SD Card (SD Memory and SDIO). SD Association (SDA)...
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Training Insights – Webinar – Automating Bug Tracking with Verisium Debug and...
The Verisium Debug platform is optimized for scalability, supporting debugging of simulation runs and emulation, where support for loading large source files and handling huge amounts of probe data is...
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Lightelligence Accelerates DFT Simulation Using Cadence Xcelium Multi-Core
The growing design complexity of today’s system on chips can result in long hours, days, and even weeks of design for testability (DFT) simulations. As these tend to occur at the end of an...
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Streamlining Your Verification Environment with Xcelium ML
When it comes to projects that involve cover groups and properties, and tests that utilize randomization, it can be challenging to ensure that the desired coverage goals are achieved. Coverage merging...
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How to Maximize Productivity and Lower Cost for Enterprise Prototyping
Semiconductor chips are often produced as application-specific integrated circuits (ASICs) for high-volume electronic devices. It is critical to ensure high quality to avoid the added costs of finding...
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Low-Power IC Design: What Is Required for Verification and Debug?
Low-Power Design Techniques Are Needed In today’s world, energy saving is a hot topic. All kinds of devices are pursuing low-power consumption to be ecofriendly or to lower the operating costs. To...
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Pre and Post-Silicon Verification Have Never Been Closer! Leveraging Portable...
The initial focus of the Portable Test and Stimulus Standard (PSS) was pre-silicon verification – even if the community, from the beginning, envisioned re-using pre-silicon test content in...
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Training Insights – A New Free Online Course on the Protium System for...
The Cadence Protium System is used for prototyping. It is a hardware platform that implements the design. It accelerates the execution of design and its verification.The Protium System offers the...
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Exploring World of Flash Memory: Serial, Dual, Quad, and Octal Interface
OverviewIn the world of digital data storage, flash memory has become an indispensable technology. Flash memory devices are non-volatile storage solutions that can retain data even without power. They...
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Coverage Closure – A Progression Instead of Just a Destination
The testing and verification of a complex hardware or software system, such as modern integrated circuits found in everything from smartphones to servers, can be a difficult process. One of the most...
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Training Insights: Bridging the Skill-Gap with the New Cadence Training...
The world is reeling towards AI/ML newer planes, and our EDA world is adding these technologies into their tools and rising to the occasion. This has created a lot of additional opportunities within...
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Introduction of Precoding in PCIe 6.0
What Is Precoding in PCIe?With higher speed introduced from PCIe 5.0, high 32.0 GT/s insertion loss target (-36dB) leads to a higher DFE tap ratio which, in turn, may trigger burst errors due to error...
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Accelerate Design Debugging Using Verisium Debug
Verisium Debug is an advanced debugging tool that helps engineers explore, analyze, and debug complex designs and test benches regardless of their size and language. Debugging with this tool is faster...
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Best Practices to Achieve the Highest Performance Using Cadence Xcelium Logic...
In a landscape characterized by increasingly intricate designs and rapidly diminishing time-to-market, today’s advanced verticals necessitate innovative strategies that yield exceptional performance...
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