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CadenceTECHTALK: Xcelium: The Key to Unlocking Unmatched Mixed-Signal...
Xcelium mixed-signal simulation is part of Cadence’s verification full flow. The latest on-demand CadenceTECHTALK, Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance, shows how you can...
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Understanding PCIe 6.0 Shared Flow Control
As the data rate increases in PCIe 6.0, so do the challenges. If we talk in terms of credits, higher data rate means more credits consumed. Today, as the designs are getting complex, the need to have...
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Best Practices to Achieve the Highest Performance Using Xcelium Logic...
Xcelium Logic Simulator Profile Analysis Our previous post discussed measuring parameters, switches, and profiling. This post will cover analyzing the profiler report. Auto Performance Analysis Xcelium...
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Best Practices to Achieve the Highest Performance Using Cadence Xcelium Logic...
Our previous posts in this series covered measuring parameters, switches, and profiling, as well as performing profile analysis. In this final post will examine how to analyze a basic profiler report....
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Power Up Your Low-Power Verification - A Quick Overview
Handheld devices have evolved immensely over the past decade. Today's smartphones, with their intricate arrays of sensors and computational power, far surpass their predecessors in complexity. These...
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Unraveling the PCIe.6.0 Compliance Feature
In PCI Express (PCIe) devices, there is a need for testing near-worst-case inter-symbol interference (ISI) and cross-talk so as to ensure data flow with minimal distortion and noise. To accommodate...
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Introducing PCIe's Integrity and Data Encryption Feature (IDE)
The Integrity and Data Encryption (IDE) was published in PCIe (Peripheral Component Interconnect Express) version 6.0, and it was created as a tool to protect the communication between the different...
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The Crucial Need for Synchronization with Third-Party Systems
In today’s interconnected world, businesses and organizations rely heavily on various software applications and systems to streamline their operations, manage data, and facilitate collaboration. Many...
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Verification of Integrity and Data Encryption (IDE) for CXL Devices
In continuation of our series on IDE blogs, Why IDE Security Technology for PCIe and CXL? and Verification of Integrity and Data Encryption(IDE) for PCIe Devices, this blog focuses on IDE verification...
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Enhancing Network Security with MacSec: Protecting Ethernet Communications.
The evolution of technology has led to a rapid increase in data transmission over Ethernet networks. With this growth comes the need for robust security measures to protect sensitive information. In...
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Cadence JedAI Accelerates Automotive SoC Design for Renesas
The automotive sector is experiencing substantial changes due to revolutionary trends like CASE (connected, autonomous, shared, and electrified). Semiconductor innovations are powering these...
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Why Do You Need a Simulator-Friendly Debug Tool for UVM Debug?
UVM Testbench Today In 2011, UVM1.0 was introduced to the industry. It has already been more than a decade that UVM has been used for testbench creation. The benefits of UVM are very clear. It’s a...
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USB4 Version 2.0 – Gen4 High-Speed Lane Initialization and Training
USB4 version 2.0 specifications were released by the USB Promoter Group earlier this year. These specifications enable up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in...
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Verifying Compliance During PCIe Re-Timer Testing Poses Challenges
Verifying compliance during PCIe re timer testing poses challenges. Cadence PCIe Verification IP not only overcomes the above challenges, but far exceeds them by locking accurately on truncated normal...
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Be Optimistic About Xcelium's New X-Pessimism App!
In simulation, X-Propagation has been used to track how unknown states or signals move through a design at RTL. These “Xs” can cause areas of a design to malfunction once the design has been...
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Accelerate Your Debug with Verisium - Cadence's Next-Generation Debug Solution
Debugging low-power designs is its own unique challenge in the verification field. Between confirming varying requirements across different power domains and the challenges associated with assuring...
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USB4 Version 2.0 – Link Configurations
USB4 Version 2.0 specification was released by the USB Promoter Group earlier this year. This specification enables up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in...
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Maximise Verification Reuse with Cadence Perspec System Verifier
Are You Tired of Countless Hours Manually Creating Complex System-Level Coverage-Driven Tests to Verify Your SoC? During the verification process, teams often work independently, creating test suits...
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Insights Into the Evolutions and Optimizations of PCIe 6.0
The PCIe protocol (Peripheral Component Interconnect Express) had its first generation in 2003, being a huge breakthrough in the industry by allowing up to 2.5 GT/s per lane in a serial computer...
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Leveraging AI to Optimize the Debug Productivity and Verification Throughput
The impact of semiconductors on various sectors cannot be overstated. Semiconductors have revolutionized our operations from the automotive industry to IoT, communication, and HPC. However, as demand...
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