USB4 version 2.0 specifications were released by the USB Promoter Group earlier this year. These specifications enable up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in asymmetric mode. Bringing up a high-speed link in USB4 consists of two parts. One part is the lane initialization, and the other is the link training.
Lane initialization comprises five phases, with each phase having an objective of its own. Phase 1 is about having the link know about the conditions that it is going to operate in, like the cable supporting Gen4 speed, being connected to the active cable having re-timers, and the cable supporting an asymmetric link. Phase 2 is about routers detecting any connected routers using the sideband channel.
In phase 3, a router acquires information about its link partner. This is done by reading the configuration registers of the link partner by using the sideband AT transactions. Specifically, the link operates in Gen4 speeds, if the lane adapters of both sides support Gen4 speed, the connecting cable supports Gen4 speed, and both lanes are enabled on each side of the link. If the link operates in Gen4 speed, then RS-FEC is always enabled.
After the lane initialization, whether the link will operate as a symmetric link or asymmetric (3 Tx/1 Rx or 3 Rx/1 Tx) link is determined in phase 3.
In phase 4, broadcast RT transactions are exchanged with the negotiated parameter values of the previous phase. Subsequently, high-speed link transmission starts at the negotiated link speed.
If it is Gen4, the LFPS handshake is used as part of the high-speed link activation. After the LFPS handshake, Gen4 TS1 with the indication field as 1 is exchanged. Finally, the receivers also get enabled. Then, the USB4 port goes to phase 5, and transitions the lane adapters FSM to a high-speed training state.
In phase 5, the TxFFE negotiation between the link partners takes place. There are separate sideband negotiations for PAM2 and PAM3 equalization flow, which are based on writes instead of polling reads to reduce the handshake overhead.
The indication to proceed to the next stage on high-speed is sent as part of the training sequences transmitted during link training instead of sideband Rx Locked.
Following the exit from the CLd state after the completion of phase 4, the lane adapters FSM switch to training.TS1 sub-state and start the Gen4 training flow. The training of a Gen4 Link uses Gen4-specific training sequences (Gen4 TS1, TS2, TS3 and TS4), instead of ordered sets.
Each Gen4 TS comprises a header and a pseudo random sequence. The header of a Gen4 Training Sequence uses PAM2 signaling, while the pseudo random sequence uses PAM2 signaling for TS1 and PAM3 signaling for TS2, TS3, and TS4.
Each training sub-state serves a different part of the link training: TS1 – for PAM2 TxFFE, TS2 – for PAM3 TxFFE, TS3 – for clock switch on re-timers, TS4 – for SSC and scrambler activation. After sending the last Gen4 TS4, lane adapters activate RS-FEC encoding, pre-coding, and scrambling, and they transition to CL0, with both lanes together acting as an aggregated link. The link is now ready for sending and receiving transport layer traffic.
USB4 VIP supports a comprehensive set of new features of USB4 version 2.0. These features are enabled on the existing architecture of USB4 VIP. This allows the current users to easily enable the USB4 version 2.0 features in their existing USB4 verification environment.
Cadence has a mature Verification IP solution for the verification of various aspects of USB4 version 2.0 and version 1.0 design, with verification capabilities provided to do a comprehensive verification of these.