Verifying Compliance During PCIe Re-Timer Testing Poses Challenges

Verifying compliance during PCIe re timer testing poses challenges. Cadence PCIe Verification IP not only overcomes the above challenges, but far exceeds them by locking accurately on truncated normal compliance pattern, allowing checkers and counters on them, and supports more skew than spec permitted. All this is available by enabling a simple configurable compliance setting provided as part of Application Programming Interface (API) to customer. This feature has been successfully deployed and helped customers verify their Re-timer Design Under Test.(read more)