As the data rate increases in PCIe 6.0, so do the challenges. If we talk in terms of credits, higher data rate means more credits consumed. Today, as the designs are getting complex, the need to have more credits arises. Hence to address this issue, shared credit pool is introduced in PCIe 6.0.
What Is Shared Flow Control?
As the name applies, this means credit shared between two or more VCs.
Here are the latest updates defined for shared flow control in PCIe 6.0:
- The VC now has
- One dedicated pool of credits (old/standard credits)
- One shared pool of credits
- TLPs can consume dedicated or shared credit
- Both types of credits are initialized independently
- VC0 is initialized and sets the initial values for the shared pool.
- Later other VCs initialize and add to the shared pool.
When shared flow control is used, initially, VC0 is initialized automatically by hardware with a dedicated FC credit pool and a shared FC pool. As system software enables other VCs, the enabled VCs are also initialized with a dedicated FC credit pool and a shared FC pool per VC. The shared FC credits for additional VCs expand the shared FC pool available to all VCs (and are permitted to be zero when the appropriate shared FC credits were granted earlier). When only a single VC is supported, there is a single “shared” credit pool, and VC0 is initialized with zero dedicated credits.
For ports that support flit mode, transmitters are required to support shared FC, and receivers are optionally permitted to support shared FC. Receivers that support shared FC must do so for all virtual channels.
It is optional for a receiver to implement but mandatory for a PCIe 6.0 device to support as a transmitter.
FC initialization remains the same as before. If sharing is enabled on either side, VC7 and VC0 automatically initialize at link up.
Changes in DLCMSM
There is an important update for DLCMSM if shared flow control is used. For non-flit mode, everything remains as the previous generations of PCIe specification. For flit mode, a new requirement for shared INIT_FCs is introduced:
Devices now are supposed to send shared INIT_FCs (P, NP, CPL) in addition to the dedicated ones.
- Non-flit mode (same as earlier): 3 Init FC DLLPs must be exchanged
- P, NP and CPL
- Flit-Mode: 6 Init FC DLLPs must be exchanged (added 3 for Shared)
- Dedicated (P, NP and CPL)
- InitFC1-P [dedicated] (first)
- InitFC1-NP [dedicated] (second)
- InitFC1-Cpl [dedicated] (third)
- Shared (P, NP and CPL)
- InitFC1-P [shared] (fourth)
- InitFC1-NP [shared] (fifth)
- InitFC1-Cpl [shared] (sixth)
How to Identify the New Type in DLLP?
In flit mode, bit 3 of byte 0 (Rsvd earlier) for InitFC1 is now used to indicate if a DLLP stands for
- Shared credits = 0
- Dedicated credits = 1
In non-flit mode, the bit keeps reserved
What Are the Benefits of Using Shared Flow Control?
In flit mode, the shared FC mechanism can be used to reduce VC resource requirements. When shared FC is used, there are two sets of resources associated with each VC: a (typically small) pool of dedicated resources associated independently with each FC/VC (to avoid deadlock by allowing the transmitter to transmit at least one TLP in that VC/FC using only dedicated credit(s)), and a portion of the (typically larger) pool of shared resources.
The shared flow control enables the reduced cost implementation of multiple virtual channels by allowing common sets of resources to be shared. However, cost and complexity are increased relative to the use of only dedicated credits, the need to have shared structures. The shared flow control usage limit mechanism also allows system software to manage the allocation of shared FC by transmitters, for example, to support Quality of Service (QoS) policies, thus addressing the efficient need for high performance.
More Information
- For more info on how Cadence PCIe Verification IP and TripleCheck enable users to confidently verify these new disruptive changes, see our VIP for PCI Express, VIP for Compute Express Link, and TripleCheck for PCI Express
- For more information on PCIe in general and on the various PCI standards, see the PCI-SIG website.
- For more information on PCIe 6.0 new features, please visit PCIeLaneMargin, PCIe6.0LaneMargin, PCIe6.0Gen6EQ.