Xcelium mixed-signal simulation is part of Cadence’s verification full flow. The latest on-demand CadenceTECHTALK, Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance, shows how you can accelerate your mixed-signal simulations with real number modeling (RNM) and EEnet in the Xcelium Logic Simulator.
Presented by Shekar Chetput and Raj Mitra of Cadence, this webinar will give you an overview of market trends around mixed-signal verification and RNM. There’s also a deeper dive into the electronics side of things with a look at some of the tool enhancements being worked on to improve user productivity, debugging, usability, and profiling.
Some of the challenges faced during mixed-signal design are also talked about in the webinar, such as:
- As mixed-signal designs get larger, SystemVerilog real number modeling (SVRNM) is used to switch out analog/spice blocks in order to increase simulation speed
- Properly creating SVRNM models is challenging and time-consuming
- Analog designers need a way to model electrical circuit behavior in SVRNM effectively
The webinar also covers some of the wider initiatives around Cadence’s Verisium Debug and the expansion into RNM adjacency. Towards the end, the benefits of RNM in mixed-signal projects are covered, and some resources for mixed-signal support are shared, which are available on the Cadence website.
The Xcelium Simulator helps teams in achieving digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows. Watch the on-demand webinar to learn more about how Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models. Learn more about Xcelium Simulation.