Clik here to view.
Ethernet Encryption: Harnessing the Power of IPSec Shields
In the ever-expanding domain of interconnected devices and digital communication, ensuring the security of data transmission has become paramount. One robust solution that stands at the forefront is...
View ArticleClik here to view.
Revolutionize System Verification Flow with a Holistic Approach
The increasing functionality of designs is leading to a noticeable rise in the complexity and efforts needed for their verification. The surge in verification efforts is not confined to hardware...
View ArticleClik here to view.
Automate Regression Failure Triage with the Cadence Verisium
Have you ever experienced the frustration of fixing a bug during the design stage only to discover additional bugs while trying to fix the existing one? As a verification engineer, this can be a common...
View ArticleClik here to view.
Navigating Cache Coherence: The Back-Invalidate Feature in CXL 3.0
In the rapidly evolving landscape of data centers, ensuring cache coherence in multi-host environments is imperative. The Compute Express Link (CXL) 3.0 specification introduces a robust mechanism...
View ArticleClik here to view.
Building Verification Infrastructure for Complex PCIe Verification
IntroductionPCIe (Peripheral Component Interconnect Express) is a high-speed serial interconnect that is widely used in consumer and server applications. Over generations, PCIe has undergone...
View ArticleClik here to view.
DisplayPort 2.1 vs DisplayPort 1.4: A Detailed Comparison of Key Features
DisplayPort is a digital display interface developed by the Video Electronics Standards Association (VESA) for connecting a video source to a display device. It is known for its high bandwidth and...
View ArticleClik here to view.
Unraveling PCIe 6.0 Loopback and Digital Near-End Loopback Feature
PCIe spec has given a specific LTSSM state named Loopback, which is intended for test and fault isolation use.Basically, it gives a mechanism that involves looping back the data that was received in...
View ArticleClik here to view.
Understanding Embedded USB2 (eUSB2) and its usage
The need for higher processing power and lower power consumption are driving processors and System on Chip (SoC) to more advanced lower process nodes. For SoCs operating at 1.2V supply that are...
View ArticleClik here to view.
What Is Viral in CXL 3.0?
Introduction to CXL 3.0CXL 3.0 is an open-standard interconnect technology that builds upon PCIe 6.0 to facilitate high-speed communication between CPUs and peripheral devices. With a doubled bandwidth...
View ArticleClik here to view.
Weak Verification Plans Lead to Project Disarray - How to Fix That
The purpose of the verification plan, or vplan as we call it, is to capture all the verification goals needed to prove that the device works as specified. It’s a big responsibility! Getting it right...
View ArticleClik here to view.
Training Insights – A Brand New Free Online Course on UCIe VIP Introduction
The Cadence VIP portfolio is used to provide various standard protocol VIPs for testing the DUT with respective protocol interfaces. All these VIPs are released together as VIPCAT release, which is...
View ArticleClik here to view.
Verifying SoC BootROM Using Standard Verification Techniques
BootROM is still found in system-on-chip (SoC) designs, especially where security concerns rule out the use of booting from off-chip, non-volatile memory. While verification strategies for RTL are...
View ArticleClik here to view.
Training Insights: Reaching your Verification Closure Using Cadence Verisium...
For a while now, Cadence has led the Verification Planning and Management (VPM) domain in the EDA Industry. Cadence’s innovative and dynamic Metric-Driven Verification Methodology, or MDV, forms the...
View ArticleClik here to view.
Lightmatter Matters - Photonics-Based Verification with Xcelium Mixed-Signal App
Traditionally, analog mixed signal (AMS) verification works by utilizing a connection between an RTL simulator, like Xcelium, and an analog simulator, like Spectre. Xcelium uses an R2E (real to...
View ArticleClik here to view.
Pre-Silicon Software Execution and Performance Validation – A Case Study
In a persistent trend, shrinking IC geometries and higher levels of integration are leading to SoCs packed with increasingly more functionality over time. Much of this functionality is implemented in...
View ArticleClik here to view.
Verisium SimAI: Machine Learning for Efficient Design Verification
Are you tired of spending hours on tedious tasks like debugging and coverage closure in your design verification process? Do you want to reduce respins and increase productivity? Look no further than...
View ArticleClik here to view.
Beyond Gigabit: Navigating the Terrain of 1600G Ethernet Networks
In the ever-evolving landscape of networking technologies, the arrival of 1600G Ethernet represents a quantum leap forward, pushing data transmission speeds to unprecedented levels. In this blog post,...
View ArticleClik here to view.
Navigating the Complexity of Address Translation Verification in PCI Express 6.0
The Address Translation Service (ATS) is a crucial process in the Peripheral Component Interconnect Express (PCIe) 6.0 architecture. It plays a pivotal role in ensuring that different processes or...
View ArticleClik here to view.
The Year That Was: Training Insights Training Bytes Blog and Video Highlights...
As we welcome 2024 now we will not miss to look back at our most-viewed blogs of the year and give an overview what else happened in our world of Education throughout the year.During 2023 we published...
View ArticleClik here to view.
Flash Memory Demystified: Nor Flash Vs. Nand Flash
In the world of flash memory, two primary types dominate the market: NOR flash and NAND flash. While they both serve as essential components in various electronic devices, they differ significantly in...
View Article