Clik here to view.
Cadence Introduces the Industry’s First GDDR7 Verification Solution
GDDR7 Introduction In February 2024, JEDEC announced the successor to GDDR6 with many new features and a big leap in terms of operating speed. GDDR7 is a high-speed synchronous graphic DRAM with a...
View ArticleClik here to view.
LPDDR5X Opening New Markets for Low-Power DRAMs
Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor market. This blog post talks about the evolutions of LPDDR DRAMs leading to the latest published standard of...
View ArticleClik here to view.
Riding the AI Wave Using HBM (High Bandwidth Memory)
The ever-increasing innovations in artificial intelligence (AI) are revolutionizing the future, be it in self-driving cars, manufacturing, finance, education, and healthcare. AI, in simple terms means...
View ArticleClik here to view.
Serial NAND Flash: New Octal SPI Dual Data Rate Capabilities
Serial NAND Flash NAND Flash has been in a constant battle to prove its competitive edge over the more prevalent NOR Flash and find a path to break into the code storage market. Delegated for use as...
View ArticleClik here to view.
Testing and Training HBM (High Bandwidth Memory) DRAM Using IEEE 1500
HBM is a JEDEC (Joint Electron Device Engineering Council) standard-defined DRAM (Dynamic Random Access Memory) with a 3D-stacked memory architecture that reduces power consumption and has a small form...
View ArticleClik here to view.
Cadence Memory Models - The Gold Standard
In today’s world, we’ve been seeing an unprecedented rise in the use of “data” with the advent of new technology like AI, ML, data mining, crypto, graphics for gaming, etc. Any data processing,...
View ArticleClik here to view.
RISC-V: Democratizing Innovation in CPU Design
RISC-V has emerged as a groundbreaking force in the semiconductor industry, fundamentally changing the CPU design and manufacturing landscape. By providing an open standard instruction set architecture...
View ArticleClik here to view.
Cooking Up Better Performance for Arm-Based SoCs
With increasing complexity, ascertaining performance in Arm-based SoCs design has become challenging, as it involves system-wide protocols connecting multiple IP in collaboration to deliver the...
View ArticleClik here to view.
Integrating Coherent RISC-V SoCs: Advanced Solutions with Perspec
In the rapidly evolving Systems on Chips (SoCs) landscape, the need for more efficient, powerful, and scalable solutions is ever-present. The RISC-V architecture, known for its open-source licensing...
View ArticleClik here to view.
Exploring the Security Framework of RISC-V Architecture in Modern SoCs
Introduction to System on Chip (SoC) SecurityIn the rapidly evolving world of technology, System-on-chip (SoC) designs have become a cornerstone for various applications, from automotive and mobile...
View ArticleClik here to view.
USB4 Version 2.0 – Low Power with Gen4 Link
USB4 Version 2.0 specification was released by the USB Promoter Group two years back. This specification enables up to 80 Gbps link speed per direction in symmetric mode and 120 Gbps link speed in...
View ArticleClik here to view.
Training Insights: Introducing the C++ Course for All Your C++ Learning Needs!
This course, "C++ Fundamentals for Design and Verification v24.03" provides an introduction to the C++ programming language for those who want to use C++ for design or verification. To optimally...
View ArticleClik here to view.
Streamline PCIe 6.0 Switch Design with Effective Verification Strategies
The demand for PCIe 6.0 switches has surged due to the exponential growth in global data traffic. PCIe 6.0 switches play a crucial role in enabling high-performance computing (HPC) systems,...
View ArticleClik here to view.
Speedy Gate-Level Simulation with Xcelium Multi-Core - Northrup-Grumman's Story
We all know the benefits of gate-level simulation, but we also all know the pain of trying to run it. Setting up and running GLS on large designs is a huge time sink for engineers—but what if there was...
View ArticleClik here to view.
Navigating the Complexity of Address Translation Verification in PCI Express 6.0
The Address Translation Service (ATS) is a crucial process in the Peripheral Component Interconnect Express (PCIe) 6.0 architecture. It plays a pivotal role in ensuring that different processes or...
View ArticleClik here to view.
Speedy Gate-Level Simulation with Xcelium Multi-Core - Northrop-Grumman's Story
We all know the benefits of gate-level simulation, but we also all know the pain of trying to run it. Setting up and running GLS on large designs is a huge time sink for engineers—but what if there was...
View ArticleClik here to view.
Advancing Digital Verification with Dynamic Duo III's Accelerated Computing
In an era where the complexity of chip design is accelerating at an unprecedented rate, Cadence's latest innovation, the Dynamic Duo III, emerges as a beacon of advancement for chip design teams...
View ArticleClik here to view.
USB4 Version 2.0 – Gen4 Link Recovery
USB4 Version 2.0 specification was released by the USB Promoter Group two years back. This specification enables up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in...
View ArticleClik here to view.
Real Number Modeling Streamlines Mixed-Signal Verification
Semiconductor design is swiftly evolving, with mixed-signal design playing a pivotal role. This approach seamlessly integrates analog and digital circuits onto a single SoC, offering notable...
View ArticleClik here to view.
Unraveling the Newly Introduced Segmentation in PCIe 6.0
Overview The PCIe protocol evolved to its sixth generation in 2021, doubling its transfer rate to 64 GT/s compared to the previous generation and bringing new features and optimizations to move...
View Article