In today’s world, we’ve been seeing an unprecedented rise in the use of “data” with the advent of new technology like AI, ML, data mining, crypto, graphics for gaming, etc. Any data processing, storing, etc. cannot be made possible without the use of memory. Also, the flavors of memory used for different applications are different, which makes memory systems even more complex. There has been a proportional rise in the requirement for memory verification in line with the increase in the usage of memory for various data-thirsty applications.
Memories Are Omnipresent
Memories can be accessed by CPU’s, GPU’s, accelerators, or data centers. Every system has a different requirement in terms of power and bandwidth, and hence, the types of memories that are connected can be of different characteristics. For example, for CPUs, generally, DDR or LPDDR types of memory are connected since they have lower data latencies and higher storage capacity, and these characteristics help CPUs in data caching.
Memories like NOR and NAND are typically used along with the AMBA bus and are used in various electronic devices. With an upswing in technologies like 5G, IoT, etc., they are gaining lots of traction. HBM and GDDR are generally used with GPUs. With the advent of the AI era, memories with high bandwidth are best suited for bandwidth thirsty applications.
MM Topology for Controller/DFI-PHY Verification
A typical use case of MMs is in the verification of controller DUT or DFI PHY DUT. MMs check the incoming signal on Memory I/F in line with the connected memory variant.
Challenges in Verification of Memories
Verifying memory can be daunting experience because of following reasons:
- Large varieties of configurations
- Long haul list of timing parameters
- Compatibility required with multiple memory vendors
- Many functional features, including complex data and command-bus training
- Wide range of operating speed
- Multiple data width and device density support
- Multiple sub-system capacity support
The permutation and combinations of these variables can grow exponentially and can become a nightmare for a verification engineer. But verification of each of these aspects is also equally important for the functional signoff of DUT.
Cadence Memory Models (MM): “The Savior”
Cadence Memory Verification IP can be an answer to all the challenges mentioned above. Few unique capabilities of Cadence MM are listed below:
- Unique MM Capabilities include like:
- Memory initialization
- Backdoor access for reading/writing memory and control words
- Dynamically load new soma file (same or different vendor)
- Dynamically get soma values, reconfigure soma features/timings
- Runtime switches (from runtime control file) to control simulations (skip initialization/refresh/training, etc.)
- Transaction and memory callback with all required information for easy scoreboarding
- Runtime Error severity demotion
- Functional coverage, assertion coverage, and many more
- A few advanced level features are also available, like data skewing, Models I/O and board delays, inter-rank protocol checks, training and calibration modeling, temperature sensing, refresh model, etc.
- Hundreds of protocols and timing checks
- Earliest availability to new features based on ever-changing ballot and specification versions
- Support for each functional feature as defined in specifications
- Multiple configurations relating to bus-width, densities, operating speed etc. based on multiple. vendors as available on http://www.ememory.com/
- Trace debug: Remote problem resolution w/o test case; no NDA requirement as this trace file doesn’t capture any design-specific information. No need to send design environment to reproduce issues
- Capability to work with any HVLs like SV, UVM, OVM, System-C
- Making user life easy by online training, reference manual, app note, demo example, API reference manual at https://vipportal.cadence.com. And most importantly, online support: https://support.cadence.com/
- Easy debug complex protocols through some unique debug capabilities like packet tracker, waveform debugger, trace debug, etc.
PACKET TRACKER
WAVEFORM DEBUGGER
There has been an unseen rise in the advent of new memory technologies, leading to the development of new protocol standards with ever-increasing complexities. Functional verification and debugging are the two major aspects that take significant time in any project development cycle. Cadence MM can help in tackling this challenge. By effectively using Cadence MM, customer can achieve their functional verification goals in much more productive and effective ways.
More information on Cadence Memory models is available at Cadence VIP Memory Models Website.
If you have any queries, feel free to contact us at talk_to_vip_expert@cadence.com
This blog is authored by Rahil Jha and Krunal Kapadiya.