Semiconductor design is swiftly evolving, with mixed-signal design playing a pivotal role. This approach seamlessly integrates analog and digital circuits onto a single SoC, offering notable performance, size, and power efficiency advantages.
Mixed-signal broadly refers to integrated circuits (ICs) that blend analog and digital functionalities. This designation applies not only to interfaces between these domains but also to ICs containing components with both analog and digital functions. Its applications span power management systems, user interfaces like haptics, and RF applications found in cell phones, laptop battery chargers, gaming controllers, and GPS systems.
Two Worlds
Analog and digital systems develop in separate domains, each with its tools and methodologies. Digital design engineers employ HDLs such as Verilog, SystemVerilog, and VHDL, alongside digital logic simulators and hardware emulators, to create and verify their designs. Conversely, analog design engineers use specialized simulators like SPICE or FastSPICE to analyze and validate analog components. However, despite their specialization, both groups typically have limited exposure to the other's domain, including modeling languages, simulators, and emulators.
Mixed-signal designs aim to integrate these separate systems into a cohesive whole within a single system-on-chip (SoC). Achieving this requires thorough system verification to ensure proper functionality.
Design Verification
Digital verification (DV) engineers typically own design verification, armed with sophisticated tools and methodologies. These encompass Universal Verification Methodology (UVM), SystemVerilog Assertions (SVA), Unified Power Format (UPF), and Metric-Driven Verification (MDV), empowering engineers to generate test stimuli, evaluate coverage, debug designs, and run regression tests seamlessly.
Yet, how do we extend these techniques to encompass the analog realm for comprehensive verification? While it's feasible to link analog and digital simulators for Analog Mixed-Signal (AMS) simulation, the extensive inter-process communication leads to significantly slower simulation runs than pure digital verification. Consequently, AMS simulation may not always suit tasks like regression tests and an MDV flow.
Verification Limitations
A traditional solution for DV engineers is to create simple stub models that isolate the digital aspects of any analog and mixed-signal elements instead of running AMS simulations.
Using stub models enables a one-dimensional verification of digital sections. However, differing perspectives between analog and digital engineers regarding analog-digital interfaces may persist. Consequently, this divergence could contribute to design failures and expensive silicon re-spins due to preventable errors. Such errors encompass pin connection mishaps, polarity inversions, improper bus ordering, and erroneous connections to power domains.
The RNM Solution
Real number modeling borrows concepts from the analog and digital simulation domains. The most crucial point for DV engineers is that real number models (RNMs) are created in a language they already know, SystemVerilog in the case of SV-RNMs. As shown in Figure 1 below, this model allows the DV engineers to perform Digital Mixed-Signal (DMS) verification using logic simulators and hardware emulators.
Figure 1. Model and simulation accuracy vs. performance and capacity for mixed-signal simulation.
RNMs empower DV engineers to fashion models capable of handling more than binary states. These models can use intricate mathematical formulas and real number values such as 3.142 or 16.893. For example, a simplified RNM that a DV engineer could devise is an analog-to-digital converter. By using RNM, much of the complexity of the entire analog circuit can be avoided, instead allowing for the focus on real number inputs and integer outputs.
Additionally, incorporating RNM in SystemVerilog allows for detailed and accurate modeling of mixed-signal interfaces in a language familiar to DV engineers. This integration facilitates more efficient and precise verification processes and bridges the analog and digital divide. It also enables the application of UVM and functional coverage in mixed-signal contexts.
It's important to note that RNMs are versatile and can go well beyond electrical circuit models. They can also model things like sensors detecting rotation and vibration or a model of lasers interfacing with a photonics processor.
EEnet
In many cases, the DV engineers seek to include an extra level of reality into the simulation concerning specific analog and mixed-signal functions. Cadence's Xcelium, coupled with the Xcelium Mixed-Signal App, provides a customized EEnet library of parameterized RNMs that represent resistors, inductors, capacitors, diodes, transistors, and op-amps to address this situation. This allows the DV engineer to develop an accurate analog circuit model within SystemVerilog. It has been demonstrated that EEnet models can yield up to 5x runtime efficiencies and within ½% accuracy compared to their SPICE counterparts.
Figure 2. EEnet Module
Conclusion
RNMs can streamline verification in the digital domain through DMS simulation or hardware emulation, significantly outpacing the speed of AMS verification. Equally noteworthy is the compatibility of all the standard tools and techniques DV engineers use, such as UVM, SVA, UPF, and MDV, to address the design's analog and mixed-signal aspects.
Ultimately, RNMs offer DV engineers a pathway to efficiently engage in mixed-signal verification using their existing resources within their familiar domain, enabling them to perform comprehensive mixed-signal verification.
For more information on mixed-signal simulation with Xcelium, see the mixed-signal whitepaper.