USB4 Version 2.0 specification was released by the USB Promoter Group two years back. This specification enables up to 80 Gbps link speed per direction in symmetric mode and 120 Gbps link speed in asymmetric mode.
Here, we take an overview of the low power entry and exit flows in Gen4 link speed and how they have been simplified as compared to that in Gen2/Gen3 link speed.
In Gen4, the low power entry has been made uni-directional, which means that there is no need for an ACK handshake anymore, hence removing any dependency on the link partner. The low power can be symmetric (CL1 or CL2) or asymmetric (CL0s). Only CL_OFF Ordered Sets are used to enter a low power state (CL0s, CL1, CL2). Now, CL1 and CL2 can be entered only from CL0s.
The low power exit of the re-timers has been simplified by removing the CL_WAKE1 and CL_WAKE2 handshakes.
For a low power entry, a router sends CL_OFF Ordered Sets with the option to enter either CL1 or CL2, with the index set to 0 if there are no intervening re-timers. If there are re-timers in between, then the index value of the CL_OFF Ordered Sets sent by a router is incremented from 1 to the number of re-timers on the link for each set of 126 CL_OFF ordered sets.
After sending the required sequence of CL_OFF Ordered Sets on the transmitter, the initiating port shuts down.
If the initiating port of the router is already in CL0s state in its RX direction, and it earlier entered this state with CL_OFF ordered sets received with the CLx state field set to 2t (2 trit), and now it sent CL_OFF ordered sets in its TX direction with the CLx state field set to 2t, it will transition to CL2 state. If the CLx state field is set to 1t (1 trit) it will transition to the CL1 state. Otherwise, it will transition to CL0s state in its TX direction.
In the intervening re-timers, on detection of a Gen 4 CL_OFF ordered set on the receiver with an index field that matches the index given to the re-timer by the router to which the re-timer forwards the Gen 4 CL_OFF ordered set, all the enabled transmitters that forwarded the Gen 4 CL_OFF are shut down.
The transition of a re-timer channel to the CL1 and CL2 states is always after the channel on the other direction is already in the CL0s state. When entry to the CL0s state occurs with Gen 4 CL_OFF and with the CL State field set to 2t, it is referred to as ‘CL0s with the option to CL2’. Otherwise, it is referred to as ‘CL0s with option to CL1’.
For a low-power exit from the CL0s state, only the USB4 port that initiated the CL0s entry can initiate the CL0s exit. CL0s_EXIT Ordered Set is used to exit CL0s low power state. Exit from CL0s is similar to lane initialization flow, involving LFPS handshake, followed by TS1 to TS4. However, the TxFFE presets remain the same as the ones before entry to low power, and are not re-negotiated on a low power exit.
The USB4 port initiating exit from CL0s state sends LFPS burst. The receiver port sends CL0s_EXIT Ordered Sets with the CL0s Phase set to 00t, 01t, 02t, 10t, one by one, which, when detected at the initiating port, it sends TS1, TS2, TS3, and TS4 with appropriate settings of the Indication field and Counter field. After sending Gen 4 TS4 with the Counter field set to Fh, the USB4 port transitions to CL0 and activates RS-FEC encoding, scrambler, and pre-coding.
A router can initiate exit from CL1 or CL2 by sending LFPS. Each re-timer and the other router detect the LFPS and respond with LFPS. After this, the initiating router and each re-timer detect the LFPS and stop transmitting LFPS toward the other router. Then, the other router and each re-timer detect that LFPS has stopped and stops transmitting LFPS towards the initiating router.
Sometime after sending the last LFPS, routers, and re-timers start to transmit Gen 4 TS1. Sometime after receiving the last LFPS, routers, and re-timers enable their receivers. Consequently, the process for low-power exit is completed by transitioning to the CL0 state.
Cadence has a mature Verification IP solution for the verification of various aspects of USB4 Version 2.0 and Version 1.0 design, with verification capabilities provided to do a comprehensive verification of these.
You may refer to https://www.cadence.com/en_US/home/tools/system-design-and-verification/verification-ip/simulation-vip.html for more information.