In an era where the complexity of chip design is accelerating at an unprecedented rate, Cadence's latest innovation, the Dynamic Duo III, emerges as a beacon of advancement for chip design teams worldwide. The introduction of the Palladium Z3 Enterprise Emulation and Protium X3 Enterprise Prototyping platforms marks a significant leap forward, offering more than double the capacity and 1.5X faster performance than their predecessors, along with a unified compile and virtual/physical interface. This evolution is not just an upgrade; it's a revolution in how we approach the increasingly intricate process of designing and testing chips, especially in light of the trend towards chiplets and the relentless growth in transistor count.
Bridging the Gap in Chip Design and Testing
The challenges in chip design and testing have grown exponentially, driven by the surge in transistors and the complexity that chiplets introduce into the system. Keeping pace with these advancements requires emulation and prototyping platforms that are not just capable but also revolutionary. Cadence rises to the occasion with its Palladium Z3 platform for hardware verification and the Protium X3 platform for accelerated software validation. These platforms are designed to work in tandem, each excelling in different but complementary areas of the chip development and verification process.
The Palladium Z3 and Protium X3 platforms are designed for quick pre-silicon verification and validation tasks, making them ideal for dealing with complex and large devices. With innovative modular compile and debugging capabilities that allow for multiple iterations daily, they set new standards for meeting the specific needs of our customers.
The new modular compiler enables designers to complete compilation in near-constant time, which is crucial for keeping teams on track when working on extremely large chips with billions of gates. Traditional compiler approaches can take days to complete under such circumstances. In contrast, the modular compiler excels with massive designs without significantly increasing compile time. This is achieved through effective parallelization and optimizations in the compilation process, making it a practical solution for handling growing designs.
Palladium Z3 Enterprise Emulation Platform
The newly released Palladium Z3 platform introduces a new, innovative custom emulation processor designed in-house with Cadence IP. It boasts over 100 billion transistors and delivers up to 1.5X the performance of its predecessor, Palladium Z2.
This next-generation platform is designed for meticulous pre-silicon hardware debugging and can handle configurations from 16 million to an impressive 48 billion gates, effectively doubling its predecessor's capacity.
Additionally, Palladium Z3 is equipped with a suite of specialized applications to enhance various aspects of chip design. These applications provide capabilities for dynamic power analysis, 4-state emulation, digital mixed-signal emulation, and functional safety emulation, all while maintaining high accuracy and substantially improving processing speed. Such advancements are crucial for chip designers, particularly in the hyperscale/AI industry, to stay ahead in a competitive market by reducing development times and accelerating product launches.
New Palladium Apps
The introduction of domain-specific apps in the Palladium Z3 platform opens up new avenues for managing system and semiconductor design complexity. These innovations, from the 4-State Emulation app to the Dynamic Power Analysis app, ensure that chip designers have the tools they need to tackle the challenges of modern chip design head-on.
- Dynamic Power Analysis App
A massively parallel architecture for power analysis that supports multi-billion gate SoCs, this app generates power reports from the integrated power estimation app to speed up power analysis by up to 5X compared to the previous generation of DPA. - 4-State Emulation App
This app accelerates low-power verification for complex SoC designs, improving verification accuracy and low-power coverage while also enhancing overall verification throughput. - Digital Mixed-Signal Emulation App
Due to increasing software-dependent interactions, DMS emulation is essential for analog circuits that are controlled by software to ensure accuracy between RF/analog and digital stages. - Palladium Safety Emulation App
Combined with Cadence Digital Safety Verification, serial fault emulation enables high-performance safety campaign execution for ISO 26262 compliance.
Protium X3 Enterprise Prototyping Platform
The Protium X3 platform is paired with AMD Versal Premium VP1902 adaptive SoCs and stands at the forefront of advanced physical prototyping technology.
This system is tailored to accelerate the bring-up times necessary for pre-silicon software validation of intricate multi-billion gate designs. It offers scalability of up to 48 billion gates and boasts a modular compiler that can compile in under 24 hours. The Protium X3 outperforms its predecessor, the Protium X2, by 1.5X in speed and is up to 3 – 5X faster than Palladium systems. In addition to its improved performance, the Protium X3 also provides 3X the capacity per rack compared to the Protium X2, allowing for scalability from 40M gates to 48B ASIC gates and enabling scaling to more racks than before.
One of the most groundbreaking aspects of the Dynamic Duo III is the seamless integration between the Palladium Z3 and Protium X3 platforms. With a unified compiler and common virtual and physical interfaces, Protium delivers a 3 to 5X faster runtime from Palladium, ideally suited for software workloads. Additionally, chip designers can accelerate the migration process, reducing bring-up time to as short as two weeks. These advancements facilitate rapid prototyping and early-stage system verification.
Setting a New Standard in Chip Design Excellence
The Palladium Z3 and Protium X3 systems are more than just hardware; they embody Cadence's commitment to pushing the boundaries of what's possible in chip design and verification. By providing ultimate capacity, performance, and integrated workflows, these systems set a new standard of excellence in the industry. They are tools and partners in the complex process of bringing the most advanced systems on chips (SoCs) to life.
As we look towards the future, the Dynamic Duo III stands as a testament to the innovation and ingenuity at Cadence. It's not just about meeting the demands of today's chip design challenges; it's about anticipating the needs of tomorrow and rising to meet them head-on. With the Palladium Z3 and Protium X3 platforms, Cadence is not just designing the future; it's defining it.
The Dynamic Duo III is poised to revolutionize the chip design landscape, and its impact will resonate across the industry for years to come.Learn more about how the new Palladium Z3 and Protium X3 platforms can transform your chip design and testing process.