Pre and Post-Silicon Verification Have Never Been Closer! Leveraging Portable Stimulus for Automatic Test Equipment (ATE)

The initial focus of the Portable Test and Stimulus Standard (PSS) was pre-silicon verification – even if the community, from the beginning, envisioned re-using pre-silicon test content in post-silicon. In this blog post, we will cover new use cases with PSS toward ATE: i.e., Automated Test Equipment typically used in production tests.

The Challenge

The ever-increasing design complexity of technology nodes and new packaging technologies for digital devices has led to a new class of device failures and, consequently, new testing approaches and innovative thinking to overcome the time-to-market pressure of today. These new demands are observed in all value chain steps and push the once silo-based disciplines, such as pre-silicon verification and ATE, to work together.

On the ATE side, the typical production test content is currently dominated by structural tests. However, while the structural test is the foundation for systematic test coverage according to targeted fault models, there is a growing need for functional tests to reach high volume readiness. Accordingly, there is a trend for an increasing amount of functional tests – further amplified by the rising quality expectations in diverse applications (e.g., automotive, data center, high-margin consumer products).

Well, it’s easier said than done, given the great challenges in creating functional tests on ATE:

• Typically, there is a need to convert the functional test content into a production test vector pattern which requires tooling and extensive development time
• On a typical ATE, there is no native software debugging environment, making it very difficult for the test case developer to debug any issues in support of the test engineer. Excessively long, unpredictable debug cycles are inevitable.

In pre-silicon verification, the growing device complexity motivated the creation of PSS, which brought a new abstraction layer and modularity to effectively describe tests on an SoC–level while decoupling the functional test from the engine it is executed on (simulator, emulator, etc.). This optimizes the test content creation for sub-systems, SoCs, and families of SoCs: a rich set of verification test scenarios becomes available in a reusable way.

The Concept

To highly optimize the enablement of functional tests on ATE, the following requirements were considered:

• The need for seamless SW-driven execution of unconverted functional test content on an ATE
• An ATE HW supporting functional HSIO communication
• Enhancing functional coverage closure by constraint random test content
• A native SW debugging environment instead of vector pattern compare and error reporting
• Enhancing the PSS scenario analysis with an activity trace viewer and the ability to vary test conditions to observe the impact in post-silicon.

The Solution

The flow diagram summarizes the overall solution achieved:

1. Test content creation– Through Cadence Perspec, PSS models used in pre-silicon are extended to ATE. Furthermore, the control knobs enable on-the-fly parametrization of test cases on ATE so that even novice PSS users can compose scenarios for ATE, constrain them, and set individual attributes for the PSS model to express the verification intent.
2. Interfacing to ATE SW – To manage hundreds or thousands of test executables and quickly hand over many tests from one team to another or share it between multiple company locations, a container file FDAT is an efficient interface between Cadence Perspec and SmarTEST 8 (Advantest ATE SW). The FDAT file container includes the necessary test binaries and test parameter sets, optional source code, documentation, statistical analysis tools, debug kits, and other items required for fast and reliable test execution.
3. Load and parameterize test content – Once loading the FDAT file in SmarTest 8, the ATE engine will be instrumented according to the content of the FDAT container. The high-speed IO interfaces to download the test and upload the results are activated appropriately. The user can execute test cases interactively for debugging/bring-up tasks or fully automate for high-volume data collection and production. In addition, the test parameters executed on the DUT can change during the execution without recompiling the complete test.
4. Test execution via ATE HW– The new ATE instrument Link Scale allows interaction with a Device Under Test (DUT) natively via a low pin count HSIO without the need to physically stimulate a parallel high pin count interface in DUT test mode. The functional test content delivered as an FDAT container can be downloaded by the V93000 SmarTest Software directly to the DUT without pattern conversion using the HSIO of the Link Scale instrument.
5. Debug and analysis– The collected traces can be analyzed to debug failing test cases. Through the Trace viewer in SmarTest, the validation and ATE engineers can evaluate what has happened during the execution of the functional test case on the DUT in a human-readable form.
   Furthermore, the traces can be imported into Cadence Verisum Debug (showing multiple synchronized views of the execution) and be correlated with the original PSS test, which guides the user when debugging the test case with an embedded software debug solution such as Lauterbach TRACE32. Link Scale hosts embedded software debuggers like TRACE32 that directly connect to the DUT through interfaces such as JTAG or SWD.

The Value Achieved

The enablement of a seamless flow between pre-silicon verification using Cadence Perspec and post-silicon testing using Advantest V93000 ATE in an automated and reliable way generated the following outcomes:

• The tight integration of all components allows the execution of an entire validation cycle within minutes.
• Reuse of test content from pre-silicon phase, saving a huge amount of time and effort, and leverage expertise and knowledge.
• The smooth test execution and unified SW environment on an ATE allow for an efficient transfer of test cases to characterization or production. In addition, the high automation capabilities of the ATE-based system enable constant monitoring of the device quality based on a complete set of functional tests.
• The coverage of the design can be analyzed by a defined set of parameters which can also be used to change environment conditions such as voltage or temperature to increase the device's quality further.
• Enablement of a comprehensive validation environment by automated data collection and analysis for a growing number of test cases across a large set of test conditions and devices.

Summing up, enabling functional test development to be executed on an ATE environment is finally enabled by the Portable Stimulus Standard, leveraging Cadence Perspec and Advantest Link Scale which translates to better throughput and Time to Quality (TTQ) while reducing Time to Market (TTM).

Sounds interesting? Please reach out for an in-depth conversation and live demo.

Moshik Rubin - mrubin@cadence.com

Adir Zonta - adir.zonta@advantest.com