Universal Chiplet Interconnect Express (UCIe) is a novel specification that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.
What Is a Chiplet?
A chiplet is a tiny integrated circuit (IC) with a well-defined specific functionality. One can relate this to LEGO building blocks for creating large structures.
Why Do We Need a Chiplet-Based Design?
Modern designs require high-performance computation feasible through lower nanometers (5-7nm), but still, most part of the design gives better performance with older nodes(16-28nm). The chiplet-based design approach opens opportunities to combine chiplets from different process nodes into the same package. This even results in cost reductions of specialized chips.
Possible combinations of disaggregated Chiplets
The Need for UCIe
UCIe provides a common chiplet interconnect that enables the construction of large SOCs that exceed the maximum reticle size. UCIe also allows intermixing of different components from different silicon vendors within the same package and improves the manufacturing yields by using smaller dies.
UCIe will become the generic protocol for On-Chip data transmission as its architecture includes a common Physical layer for multiple protocols. The most significant advantage is that you can change the physical or upper layers without interfering with either of them. This is due to well-defined interfaces between the different layers for easier integration with other protocols.
The UCIe specification defines three layers: Physical,Die-to-Die(D2D) Adapter,and Protocol layer. The Physical layer supports multiple lanes with varying speeds, and the Protocol layer is implementation specific and can consist of a CXL, PCIe, or proprietary Streaming protocols. UCIe leverages these to move data between chiplets. The data transfer between UCIe links is defined in terms of Flow Control Unit(FLIT) or raw data.
UCIe Layers and Components
The main features of UCIe are:
- High-Speed Interface
- Can be used with multiple protocols
- Chiplet-based design for higher yields.
Cadence Verification IP for UCIe is available to support the latest UCIe specification, allowing the simulation of different layers for IP, SOC, and system-level design verification. Semiconductor companies can start using it to fully verify their design and achieve functional verification closure on it within no time. More details are available on the Cadence Verification IP Portfolio.
For more information on UCIe in general, check the UCIe Organization website.
Stay tuned for more.
