For the past few decades, design and verification technology have made great progress. More sophisticated designs are verified with faster simulation and emulation. However, the debug is pretty much the same as 20 years ago. The most bothersome thing for engineers is why there’s no way to automate the process. What engineers typically do is, check the log file and see if there are any errors from verification tools such as simulation, linting, CDC, and so on. When an error is spotted, there are still many steps, and multiple experts need to get involved in analyzing the issue and root cause of the actual problematic point. However, life is not always that easy. Sometimes it takes several iterations to trace back and forth to get to the root cause of the problem.

Every engineer is dreaming of technology that solves problems with a single click of a button. This is, of course, is a utopia. But with evolving technology and the assistance of Artificial Intelligence (AI) and Machine Learning (ML), it is made possible to help engineers drastically reduce their valuable spent time to get to the bug as quick as possible. No hassle of bringing the waveform, manually inspecting the source codes, and finally getting to the right spot to debug.

The Challenge of Debug Today

If we look at an SoC design today, it usually comes with many protocols such as PCIe, AMBA, CXL, etc. Low power and testbench are also very common in the SoC design and verification flow. More and more tests and verifications are required in the design verification flow to ensure the quality and functions of SoC. Regression tests are often done in the verification environment to verify SoCs thoroughly. Regression tests mean that the quantity of tests can be thousands or tens of thousands in scale.

With that big scale of test quantity, the biggest challenges for engineers are obviously effort and time. From thousands of regression tests, engineers might get at least dozens of errors or more which require analysis and debug. The log file from each simulation run is usually where analysis and debug begin. However, it is still a long way to go until the real problem is identified. You can also imagine, besides the log file, it also requires relevant design data, such as source code, waveform, and schematics, to help engineers to debug and finally get to the bug.

To inspect and debug every single regression error takes a huge amount of engineers’ time. Shortening and automating the debug process are truly critical to debug productivity.

Verisium Debug and Verisium Apps

With the progression of technology, AI and ML technologies are being applied into design debug. With assistance from AI and ML technology, debug can be automated. This helps reduce the amounht of effort that engineers have to put to find the root cause of the problem.

Through the introduction of Verisium Platform and Verisium Debug, this new verification platform brings AI and ML into verification to help engineers save their efforts and time for design verification and debug.

The Verisium platform integrates Cadence’s latest JedAI platform. AI and ML technology enables new Verisium apps, including SemanticDiff, PinDown, WaveMiner, and AutoTirage, to help engineers analyze any potential changes in the design that may change the design behavior and cause problems.

With the results from AI-enabled Verisium apps, Verisium Debug can directly take the benefits from the AI technologies and display the pinpointed result to engineers. From there, it becomes very easy and straightforward to spend valuable engineer time solving the real bugs instead of spending time to setup environment and trace all the way to the actual problems.

Verisium Debug

By integrating with the AI/ML enabled Verisium Apps, Verisium Debug is the final and important step to pinpoint the bugs. Verisium Apps use AI/ML technology to help engineers to narrow down the potential problematic area. It is engineer’s job to confirm where is actually causing the problem and fix it. As mentioned in the beginning, debug really bothers the productivity of engineers. Engineers’ primary job is to design a properly functioned chip, not debug. Making debug as easy as possible is fundamentally required for all engineers. How to make debug easy? Here I’m trying to list a few things which can be considered as helping debug easy:

• Nice and intuitive GUI: The bug is already burning, there’s no time for engineer to go through manuals to understand how to run a debug tool. Straightforward use model and easy to use is a must
• Performance: No one wants to wait long to open design and simulation waveform. Don’t mention to wait for more than a minute when tracing a driver or a load
• Scalability: Same debug environment has to be used in not just RTL block level design, it should also work on a SoC level netlist, as well as from simulation and emulation. Engineer can’t predict when and where the bug will happen
• Customization: Engineer might have their own secret trick, provide flexibility to customize their debug environment is also helping for debug efficiency

Cadence just announced the latest debug platform, Verisium Debug. The Verisium Debug is brining all the benefits mentioned above. Integrating with all the verification products from Cadence, Verisium Debug provides high performance and best user experience for debugging.

By using the latest GUI framework and well-designed debug capabilities. Verisium Debug enables a “manual free” debug environment. This is very important for so-called “Smartphone Generation”. No one is reading a manual to understand how to make a tool work. Simply with a few mouse-clicks, you get your work done!

The newly introduce waveform format, VWDB (Verisium Waveform DB), provides more than 2x performance to generate and read. This also very important for debugging, because generating and reading waveform is the most critical step in the debug process. Having waveform created and visualized in waveform window as soon as possible is always what engineers are asking for.

Talking about customization, Verisium Debug provides Python based API that allows engineers to write Python programs that can access the data from Verisium Debug’s databases and also to control GUI settings and actions. With these capabilities, user can easily to customize Verisium Debug to fit into design/verification flow and make it integrated into daily working environment.

From IP to SoC level designs, Verisium Debug is a proven debug solution for Cadence verification products. Several world class semiconductor leading companies, such as Samsung, Mediatek, and ST Microelectronics have adopted Verisium Debug as their debug solution and enjoy the benefits from Verisium Debug to reduce their debug TAT. (Refer to following press release Verisium Platform)

Debug productivity has been a critical part in verification cycle. As I mentioned in the beginning, there’s no automation that allows engineers to skip steps from errors to actual bugs. With the introduction of Verisium Platform and Verisium Debug, there’s finally an AI assisted debug strategy that can really help engineers to skip many steps all the way to the actual causes of the issues. Now engineers can really focus on real problems!

To understand more about Verisium Debug, please visit: Verisium Debug Website.