The PCI-SIG Developers Conference 2024 is poised to be the premier event for professionals in the computing and technology sectors. Designed to unite experts and innovators worldwide, the conference features in-depth technical sessions, workshops, and demonstrations focused on advancements in PCI technology. This year's conference was in Santa Clara on June 12 and 13.
Virginia Satyro and Geeta Arora from the Cadence VIP team delivered booth and paper presentations. Drawing from extensive research and real-world applications, their insights will shed light on the complexities and innovations of PCIe 6.0 technology.
This blog post explores their paper, "Demystifying Verification of PCIe 6.0 Equalization."
Introduction to PCIe 6.0
PCI Express (PCIe) has continuously evolved to meet the growing demands for faster data transfer rates. PCIe 6.0, the latest iteration, introduces several significant changes to enhance performance. However, these advancements also bring new challenges, particularly concerning signal integrity and equalization. This paper comprehensively overviews these challenges and offers practical solutions for effective verification.
Understanding PAM4 Modulation
One of the most notable changes in PCIe 6.0 is the shift from Non-Return to Zero (NRZ) modulation to Pulse Amplitude Modulation 4-Level (PAM4) to achieve higher data rates. This new modulation scheme doubles the data throughput by encoding two bits of information per unit interval instead of one, effectively doubling the throughput while maintaining the same signal frequency. However, this comes at the cost of increased signal sensitivity to noise and burst errors.
The Image explains how PAM4 modulation significantly impacts signal quality with its four differential voltage levels, leading to a higher Bit Error Rate (BER). While previous generations required a BER of at least 10^-12, PCIe 6.0 must contend with a First Bit Error Rate (FBER) of less than 10^-6. This substantial increase in BER necessitates more sophisticated equalization techniques to maintain data integrity at 64GT/s.
Equalization at 64GT/s
Equalization for 64GT/s introduces notable advancements to optimize performance and efficiency. One significant option is bypassing intermediate speed equalization, moving directly from 2.5GT/s to the highest supported speed (e.g., 32GT/s), and then performing equalization at that speed before transitioning to 64GT/s.
This approach expedites the process. Another key feature is the option to eliminate equalization if both devices support the NO EQUALIZATION NEEDED protocol. This is beneficial in controlled environments where coefficient values might be preset, simplifying the process. The 64GT/s speed also debuts the TS0 training sequence, incorporating new encoding rules and ensuring optimal initial communication using differentiated voltage levels for increased reliability.
Furthermore, the equalization process at 64GT/s involves a more complex four-tap equalizer, transitioning from the three-tap equalizer used in previous generations. This change is essential for handling the higher frequencies and new 1b/1b encoding at 64GT/s. The ordered sets TS0, TS1, and TS2 have also been redefined to ensure robust communication during the initial equalization phases. Additionally, the timing for phases 2 and 3 has been doubled to 48 milliseconds to account for the increased difficulty in fine-tuning. Although the equalization process at this higher speed introduces several new elements and changes, it maintains a structure similar to that of lower speeds, ensuring consistency and reliability.
Training Sequences
Training sequences TS1 and TS2 in the 1b/1b format play crucial roles in the initial flow of LTSSM (Link Training and Status State Machine) states and the recovery process. Key differences in their formats include the scrambling of symbols 1 to 6, with symbol 0 remaining unscrambled. Symbol 7 can either be scrambled or unscrambled, depending on its parity and DC balance: it remains unscrambled if it represents DC balance, and it is scrambled if it represents even parity bits. The Equalization Control bit continues to carry various values such as presets, use-a-preset bit, reject coefficients bit, equalization redo, and coefficients, which have been reallocated for this format, and with TS1, four voltage levels are used during transmission.
In the TS0 sequence, the Equalization Control is used for phase advertisement, with symbols renamed Equalization Bytes. These bytes help communicate coefficients and their values, which vary in size to define multiplier values in the 4-tap equalizer. Specifically, C0 has larger values due to its more significant impact on the signal. Each byte includes only four important bits, as odd bits carry the essential data. Proper decoding of TS0 by DUT/VIP is vital, and phase and state transition rules during recovery and equalization must be strictly adhered to.
Implementing solutions to mitigate verification challenges involves creating checkers to verify all symbols of TS0, ensuring the correct functioning of scrambling, and monitoring phase and LTSSM state transitions. Error injection tests can help verify TS0 transmission and reception accuracy, with the monitor set to trigger errors if incorrect handling is detected. Additionally, employing a monitor to track all transitions and report protocol violations is crucial. For instance, error injection to corrupt even bits should be recognized by the DUT, emphasizing the need for robust error detection capabilities to ensure the seamless operation of the Equalization process at 64GT/s.
Equalization Phases
The Equalization process involves transitioning from lower data rates up to the desired 64GT/s speed, but it does not support a direct move from 2.5GT/s or 5GT/s to 64GT/s. All equalization at the 64GT/s rate must begin from 32GT/s. During the Recovery phase at 32GT/s, downstream ports advertise the Presets for the Upstream port to use once the 64GT/s speed is reached.
The equalization flow diagram is illustrated here. Initially, the Downstream port advertises phase 1 while the Upstream port advertises phase 0, exchanging TS0s. The Upstream port waits until it recognizes ordered sets and achieves a BER of at least 104 before proceeding to phase 1. The Downstream port also evaluates for phase 1 recognition. If necessary, it proceeds to phases 2 and 3 by advertising TS1s. In phase 2, downstream tuning occurs, where the Downstream port requests the Upstream port to evaluate the signal quality and adjust coefficients if needed, repeating the process within a 48 ms window.
Upon achieving satisfactory signal quality, the Upstream port transitions to phase 3 by sending TS1s, allowing the Downstream port to evaluate the upstream signal and fine-tune accordingly. Both sides will send TS2s, followed by IDLE Flits, before finally entering L0. This structured flow ensures efficient and effective equalization.
Autonomous vs. Software-Based Equalization
Another key aspect is the difference between autonomous and software-based equalization mechanisms. Autonomous equalization relies on the hardware's built-in capabilities to adjust signal parameters in real time, while software-based equalization requires external control via software algorithms. While autonomous equalization offers faster adjustments, software-based approaches provide greater flexibility and customization. A hybrid approach is recommended, leveraging the strengths of both methods to achieve optimal signal quality.
Test Scenarios and Checkers
Several test scenarios and checkers designed explicitly for 64GT/s verification were analyzed to validate the effectiveness of equalization techniques. These scenarios simulate various operational conditions, enabling engineers to identify and address potential issues before deployment. The checkers provide real-time feedback, ensuring that the equalization process adheres to the stringent requirements of PCIe 6.0.
In summary, the paper highlighted the rapid advancements in PCI Express technology and the critical role of equalization in maintaining signal integrity. For those eager to explore the intricacies of PCIe 6.0 and enhance their verification processes, staying updated with the latest research and best practices is essential.
Curious to learn more? PCI-SIG members can explore the full paper on the PCI-SIG website. For those looking to delve deeper into the capabilities of Cadence PCIe Verification IP and TripleCheck, we invite you to discover how these tools enable confident verification of groundbreaking technology changes. Enhance your understanding by visiting our pages on VIP for PCI Express, VIP for Compute Express Link, and TripleCheck for PCI Express.
Let's embark on this journey of innovation together.